公开(公告)号：US11005454B1

公开(公告)日：2021-05-11

申请号：US16793010

申请日：2020-02-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Dzung T. Tran ,  Sushama Davar

IPC: H03K3/013 ,  H03K3/3568 ,  H03K19/017 ,  H03K19/003

Abstract: A disclosed pre-driver circuit includes multiple signal generation stages configured to receive different bias voltages from local switching bias circuit(s). In some embodiment, pre-driver circuit has multiple switching bias circuits, each with a bias voltage node connected to a corresponding stage. In other embodiments, the pre-driver circuit has a single switching bias circuit with multiple bias voltage nodes and a multi-input/multi-output multiplexor with inputs connected to the bias voltage nodes and outputs connected to the stages. The switching bias circuit(s) and a primary inverter in each stage all receive the same input signal. When this input signal transitions, the switching bias circuit(s) supply bias voltages to the stages and the primary inverters turn on in sequence and slowly, thereby ensuring that pre-driver signals generated by the different stages transition in sequence and at a relatively slow rate. Once the last pre-driver signal transitions, the switching bias circuit(s) turn off.

公开(公告)号：US12047068B2

公开(公告)日：2024-07-23

申请号：US18080378

申请日：2022-12-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Dzung T. Tran ,  Shivraj G. Dharne

IPC: H03K19/01 ,  H03K19/003 ,  H03K19/0185

CPC classification number: H03K19/018521 ,  H03K19/00315 ,  H03K19/00361

Abstract: The present disclosure relates to a structure including a level shifter circuit which receives an input signal and at least one voltage reference signal and outputs at least one level shifted output signal, a pre-driver circuit which receives the at least one level shifted output signal and outputs at least one pre-driver output signal, the pre-driver circuit including at least one delay circuit, and a main driver circuit which receives the at least one pre-driver output signal and outputs a main driver output signal.

公开(公告)号：US20220182058A1

公开(公告)日：2022-06-09

申请号：US17112456

申请日：2020-12-04

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Dzung T. Tran ,  Shibly S. Ahmed

IPC: H03K19/0185 ,  H03K19/20

Abstract: Embodiments of the disclosure provide an input output (IO) structure in which complimentary nodes of a level shifter are utilized to logically block the output of the IO structure from switching until both power supplies to the IO structure are powered up. An illustrative level shifter includes: a cross-coupled pair of PFETs configured to output complimentary voltage values at a first node and a second node; a control circuit configured to select which of the complementary voltage values are output to the first node and second node; a logic inverter having an input coupled to the first node and an output coupled to a third node; and a NAND gate having inputs coupled to the second node and third node and that generates a level shifted output.

公开(公告)号：US20240274161A1

公开(公告)日：2024-08-15

申请号：US18166544

申请日：2023-02-09

Applicant: GlobalFoundries U.S. Inc.

Inventor： Dzung T. Tran ,  Navneet K. Jain

IPC: G11C5/14 ,  G01R19/165

CPC classification number: G11C5/147 ,  G01R19/16519

Abstract: Embodiments of the disclosure provide a structure and method to ground a reference voltage generator based on a detected supply voltage. A circuit structure according to the disclosure includes a pass gate. The pass gate includes a pair of transistors each coupled to an input signal. One of the pair of transistors of the pass gate includes a gate coupled to a static reference voltage. An inverter couples an output from the pass gate to a device node. The inverter includes a drain terminal, a gate terminal, and a back-gate terminal coupled to ground.

公开(公告)号：US20240195416A1

公开(公告)日：2024-06-13

申请号：US18064978

申请日：2022-12-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Dzung T. Tran ,  Deepti A. Pant ,  Shibly S. Ahmed

IPC: H03K19/003

CPC classification number: H03K19/00361 ,  H03K19/00315

Abstract: Disclosed is an input buffer with hysteresis-integrated voltage protection devices for avoiding violations of maximum gate-to-source voltage limitations when the maximum input voltage is greater than the maximum gate-to-source voltage limitation. The input buffer includes a chain of transistors including two P-channel FETs (PFETs) and two N-channel FETs (NFETs). The data input to the input buffer controls the gates of the transistors in the chain so the data output from the input buffer at the junction between the PFETs and NFETs is inverted. The input buffer also includes a hysteresis feedback loop to prevent noise-induced switching of the output. The hysteresis feedback loop also includes voltage protection devices integrated therein to avoid maximum gate-to-source violations when the loop results in a hysteresis voltage being fed back into the chain at the source region of a transistor in the chain. Also disclosed is a receiver incorporating the input buffer.

公开(公告)号：US11368155B1

公开(公告)日：2022-06-21

申请号：US17112456

申请日：2020-12-04

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Dzung T. Tran ,  Shibly S. Ahmed

IPC: H03K19/0175 ,  H03K19/0185 ,  H03K19/20 ,  H03K19/003

Abstract: Embodiments of the disclosure provide an input output (IO) structure in which complimentary nodes of a level shifter are utilized to logically block the output of the IO structure from switching until both power supplies to the IO structure are powered up. An illustrative level shifter includes: a cross-coupled pair of PFETs configured to output complimentary voltage values at a first node and a second node; a control circuit configured to select which of the complementary voltage values are output to the first node and second node; a logic inverter having an input coupled to the first node and an output coupled to a third node; and a NAND gate having inputs coupled to the second node and third node and that generates a level shifted output.

公开(公告)号：US20250080091A1

公开(公告)日：2025-03-06

申请号：US18459522

申请日：2023-09-01

Applicant: GlobalFoundries U.S. Inc.

Inventor： Dzung T. Tran ,  Navneet K. Jain ,  Uttam Saha

IPC: H03K3/037 ,  H01L27/092

Abstract: A disclosed flip-flop includes primary and secondary sections connected to switchable and continuous power supplies, respectively. The primary section includes logic outputting first control signals, a primary latch controlled by the first control signals, and a data output device connected to an output terminal of the primary latch. The secondary section includes logic outputting second control signals and a secondary latch. A first transmission gate controlled by the second control signals is connected between the output terminal of the primary latch and an input terminal of the secondary latch. A second transmission gate controlled by the first and second control signals is connected between output and input terminals of the secondary latch. In a normal mode, both sections receive power and the first transmission gate is conductive. In a retention mode, the primary section is powered down, the first transmission gate is non-conductive and the second transmission gate is conductive.