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公开(公告)号：US20190378239A1
公开(公告)日：2019-12-12
申请号：US16547801
申请日：2019-08-22
Applicant: Google LLC
Inventor： Qiuling Zhu , Ofer Shacham , Albert Meixner , Jason Rupert Redgrave , Daniel Frederic Finchelstein , David Patterson , Neeti Desai , Donald Stark , Edward Chang , William R. Mark
Abstract: An apparatus is described. The apparatus includes an image processing unit. The image processing unit includes a plurality of stencil processor circuits each comprising an array of execution unit lanes coupled to a two-dimensional shift register array structure to simultaneously process multiple overlapping stencils through execution of program code. The image processing unit includes a plurality of sheet generators respectively coupled between the plurality of stencil processors and the network. The sheet generators are to parse input line groups of image data into input sheets of image data for processing by the stencil processors, and, to form output line groups of image data from output sheets of image data received from the stencil processors. The image processing unit includes a plurality of line buffer units coupled to the network to pass line groups in a direction from producing stencil processors to consuming stencil processors to implement an overall program flow.
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公开(公告)号：US09965824B2
公开(公告)日：2018-05-08
申请号：US14694828
申请日：2015-04-23
Applicant: Google LLC
Inventor： Qiuling Zhu , Ofer Shacham , Albert Meixner , Jason Rupert Redgrave , Daniel Frederic Finchelstein , David Patterson , Neeti Desai , Donald Stark , Edward T. Chang , William R. Mark
Abstract: An apparatus is described. The apparatus includes an image processing unit. The image processing unit includes a network. The image processing unit includes a plurality of stencil processor circuits each comprising an array of execution unit lanes coupled to a two-dimensional shift register array structure to simultaneously process multiple overlapping stencils through execution of program code. The image processing unit includes a plurality of sheet generators respectively coupled between the plurality of stencil processors and the network. The sheet generators are to parse input line groups of image data into input sheets of image data for processing by the stencil processors, and, to form output line groups of image data from output sheets of image data received from the stencil processors. The image processing unit includes a plurality of line buffer units coupled to the network to pass line groups in a direction from producing stencil processors to consuming stencil processors to implement an overall program flow.
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公开(公告)号：US10789505B2
公开(公告)日：2020-09-29
申请号：US15631906
申请日：2017-06-23
Applicant: Google LLC
Inventor： Ofer Shacham , David Patterson , William R. Mark , Albert Meixner , Daniel Frederic Finchelstein , Jason Rupert Redgrave
Abstract: A method is described that includes executing a convolutional neural network layer on an image processor having an array of execution lanes and a two-dimensional shift register. The executing of the convolutional neural network includes loading a plane of image data of a three-dimensional block of image data into the two-dimensional shift register. The executing of the convolutional neural network also includes performing a two-dimensional convolution of the plane of image data with an array of coefficient values by sequentially: concurrently multiplying within the execution lanes respective pixel and coefficient values to produce an array of partial products; concurrently summing within the execution lanes the partial products with respective accumulations of partial products being kept within the two dimensional register for different stencils within the image data; and, effecting alignment of values for the two-dimensional convolution within the execution lanes by shifting content within the two-dimensional shift register array.
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公开(公告)号：US10546211B2
公开(公告)日：2020-01-28
申请号：US15201204
申请日：2016-07-01
Applicant: Google LLC
Inventor： Ofer Shacham , David Patterson , William R. Mark , Albert Meixner , Daniel Frederic Finchelstein , Jason Rupert Redgrave
Abstract: A method is described that includes executing a convolutional neural network layer on an image processor having an array of execution lanes and a two-dimensional shift register. The two-dimensional shift register provides local respective register space for the execution lanes. The executing of the convolutional neural network includes loading a plane of image data of a three-dimensional block of image data into the two-dimensional shift register. The executing of the convolutional neural network also includes performing a two-dimensional convolution of the plane of image data with an array of coefficient values by sequentially: concurrently multiplying within the execution lanes respective pixel and coefficient values to produce an array of partial products; concurrently summing within the execution lanes the partial products with respective accumulations of partial products being kept within the two dimensional register for different stencils within the image data; and, effecting alignment of values for the two-dimensional convolution within the execution lanes by shifting content within the two-dimensional shift register array.
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公开(公告)号：US10531030B2
公开(公告)日：2020-01-07
申请号：US16448931
申请日：2019-06-21
Applicant: Google LLC
Inventor： Albert Meixner , Daniel Frederic Finchelstein , David Patterson , William R. Mark , Jason Rupert Redgrave , Ofer Shacham
Abstract: A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly shifting first content of multiple rows or columns of the two dimensional shift register array and repeatedly executing at least one instruction between shifts that operates on the shifted first content and/or second content that is resident in respective locations of the two dimensional shift register array that the shifted first content has been shifted into.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20190327437A1
公开(公告)日：2019-10-24
申请号：US16448931
申请日：2019-06-21
Applicant: Google LLC
Inventor： Albert Meixner , Daniel Frederic Finchelstein , David Patterson , William R. Mark , Jason Rupert Redgrave , Ofer Shacham
Abstract: A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly shifting first content of multiple rows or columns of the two dimensional shift register array and repeatedly executing at least one instruction between shifts that operates on the shifted first content and/or second content that is resident in respective locations of the two dimensional shift register array that the shifted first content has been shifted into.
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公开(公告)号：US09986187B2
公开(公告)日：2018-05-29
申请号：US15628527
申请日：2017-06-20
Applicant: GOOGLE LLC
Inventor： Albert Meixner , Daniel Frederic Finchelstein , David Patterson , William R. Mark , Jason Rupert Redgrave , Ofer Shacham
CPC classification number: H04N5/3742 , G06F5/015 , G06F12/0207 , G06F17/16 , G06T1/20 , H04N5/341
Abstract: A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly shifting first content of multiple rows or columns of the two dimensional shift register array and repeatedly executing at least one instruction between shifts that operates on the shifted first content and/or second content that is resident in respective locations of the two dimensional shift register array that the shifted first content has been shifted into.
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公开(公告)号：US20210004633A1
公开(公告)日：2021-01-07
申请号：US17028097
申请日：2020-09-22
Applicant: Google LLC
Inventor： Ofer Shacham , David Patterson , William R. Mark , Albert Meixner , Daniel Frederic Finchelstein , Jason Rupert Redgrave
Abstract: A method is described that includes executing a convolutional neural network layer on an image processor having an array of execution lanes and a two-dimensional shift register. The two-dimensional shift register provides local respective register space for the execution lanes. The executing of the convolutional neural network includes loading a plane of image data of a three-dimensional block of image data into the two-dimensional shift register. The executing of the convolutional neural network also includes performing a two-dimensional convolution of the plane of image data with an array of coefficient values by sequentially: concurrently multiplying within the execution lanes respective pixel and coefficient values to produce an array of partial products; concurrently summing within the execution lanes the partial products with respective accumulations of partial products being kept within the two dimensional register for different stencils within the image data; and, effecting alignment of values for the two-dimensional convolution within the execution lanes by shifting content within the two-dimensional shift register array.
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公开(公告)号：US10733956B2
公开(公告)日：2020-08-04
申请号：US16685388
申请日：2019-11-15
Applicant: Google LLC
Inventor： Albert Meixner , Neeti Desai , Dilan Manatunga , Jason Rupert Redgrave , William R. Mark
Abstract: An image processor is described. The image processor includes an I/O unit to read input image data from external memory for processing by the image processor and to write output image data from the image processor into the external memory. The I/O unit includes multiple logical channel units. Each logical channel unit is to form a logical channel between the external memory and a respective producing or consuming component within the image processor. Each logical channel unit is designed to utilize reformatting circuitry and addressing circuitry. The addressing circuitry is to control addressing schemes applied to the external memory and reformatting of image data between external memory and the respective producing or consuming component. The reformatting circuitry is to perform the reformatting.
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公开(公告)号：US10719905B2
公开(公告)日：2020-07-21
申请号：US16547801
申请日：2019-08-22
Applicant: Google LLC
Inventor： Qiuling Zhu , Ofer Shacham , Albert Meixner , Jason Rupert Redgrave , Daniel Frederic Finchelstein , David Patterson , Neeti Desai , Donald Stark , Edward Chang , William R. Mark
Abstract: An apparatus is described. The apparatus includes an image processing unit. The image processing unit includes a plurality of stencil processor circuits each comprising an array of execution unit lanes coupled to a two-dimensional shift register array structure to simultaneously process multiple overlapping stencils through execution of program code. The image processing unit includes a plurality of sheet generators respectively coupled between the plurality of stencil processors and the network. The sheet generators are to parse input line groups of image data into input sheets of image data for processing by the stencil processors, and, to form output line groups of image data from output sheets of image data received from the stencil processors. The image processing unit includes a plurality of line buffer units coupled to the network to pass line groups in a direction from producing stencil processors to consuming stencil processors to implement an overall program flow.
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