公开(公告)号：US20210011991A1

公开(公告)日：2021-01-14

申请号：US16509662

申请日：2019-07-12

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Christoph L. Schmitz

IPC: G06F21/44 ,  G06F21/60 ,  H04L9/32 ,  H04L9/08

Abstract: A method includes a controller detecting a signal state of a presence terminal that is associated with a bus device. The signal state is set by the bus device to indicate presence of the bus device in a connector, and the connector is connected to a bus. The method includes the controller communicating data over the bus; and in response to detecting the signal state, the controller communicating side channel data to the bus device to authenticate the data that is communicated over the bus as being provided by the controller. Communicating the side channel data with the bus device includes providing a signal to the presence terminal, which represents the side channel data.

公开(公告)号：US11379571B2

公开(公告)日：2022-07-05

申请号：US16509662

申请日：2019-07-12

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Christoph L. Schmitz

IPC: G06F21/44 ,  G06F21/60 ,  H04L9/32 ,  H04L9/08 ,  G06F21/85

Abstract: A method includes a controller detecting a signal state of a presence terminal that is associated with a bus device. The signal state is set by the bus device to indicate presence of the bus device in a connector, and the connector is connected to a bus. The method includes the controller communicating data over the bus; and in response to detecting the signal state, the controller communicating side channel data to the bus device to authenticate the data that is communicated over the bus as being provided by the controller. Communicating the side channel data with the bus device includes providing a signal to the presence terminal, which represents the side channel data.

公开(公告)号：US10324777B2

公开(公告)日：2019-06-18

申请号：US15335958

申请日：2016-10-27

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Christoph L. Schmitz ,  Thomas Donald Rhodes ,  Nicholas Mark Hawkins ,  Binh Nguyen ,  Wayne Hsu

IPC: G06F12/00 ,  G06F11/00 ,  G06F9/30 ,  G06F12/02

Abstract: An example device may include processing circuitry and a management controller. The processing circuitry may include a communications interface that includes a first register and a second register. The first register may include a freshness bit and a number of first data bits. The second register may include a number of second data bits that correspond, respectively, to the first data bits. The processing circuitry may write variously to the first data bits in response to detected events, set the freshness bit in response to the management controller reading the first data bits, and reset the freshness bit if any of the first data bits are written to. The management controller may read the first data bits, perform predetermined processing based thereon, write to the second data bits based on the predetermined processing, and request a register transfer. The processing circuitry may, in response to the management controller requesting the register transfer, transfer values of the second data bits to their respectively corresponding first data bits if and only if the freshness bit is currently asserted.

公开(公告)号：US20180121087A1

公开(公告)日：2018-05-03

申请号：US15335958

申请日：2016-10-27

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Christoph L. Schmitz ,  Tom Rhodes ,  Nicholas Mark Hawkins ,  Binh Nguyen ,  Wayne Hsu

IPC: G06F3/06

CPC classification number: G06F11/00

Abstract: An example device may include processing circuitry and a management controller. The processing circuitry may include a communications interface that includes a first register and a second register. The first register may include a freshness bit and a number of first data bits. The second register may include a number of second data bits that correspond, respectively, to the first data bits. The processing circuitry may write variously to the first data bits in response to detected events, set the freshness bit in response to the management controller reading the first data bits, and reset the freshness bit if any of the first data bits are written to. The management controller may read the first data bits, perform predetermined processing based thereon, write to the second data bits based on the predetermined processing, and request a register transfer. The processing circuitry may, in response to the management controller requesting the register transfer, transfer values of the second data bits to their respectively corresponding first data bits if and only if the freshness bit is currently asserted.