公开(公告)号：US10324777B2

公开(公告)日：2019-06-18

申请号：US15335958

申请日：2016-10-27

申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

发明人： Christoph L. Schmitz ,  Thomas Donald Rhodes ,  Nicholas Mark Hawkins ,  Binh Nguyen ,  Wayne Hsu

IPC分类号： G06F12/00 ,  G06F11/00 ,  G06F9/30 ,  G06F12/02

摘要： An example device may include processing circuitry and a management controller. The processing circuitry may include a communications interface that includes a first register and a second register. The first register may include a freshness bit and a number of first data bits. The second register may include a number of second data bits that correspond, respectively, to the first data bits. The processing circuitry may write variously to the first data bits in response to detected events, set the freshness bit in response to the management controller reading the first data bits, and reset the freshness bit if any of the first data bits are written to. The management controller may read the first data bits, perform predetermined processing based thereon, write to the second data bits based on the predetermined processing, and request a register transfer. The processing circuitry may, in response to the management controller requesting the register transfer, transfer values of the second data bits to their respectively corresponding first data bits if and only if the freshness bit is currently asserted.

公开(公告)号：US20180121087A1

公开(公告)日：2018-05-03

申请号：US15335958

申请日：2016-10-27

申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

发明人： Christoph L. Schmitz ,  Tom Rhodes ,  Nicholas Mark Hawkins ,  Binh Nguyen ,  Wayne Hsu

IPC分类号： G06F3/06

CPC分类号： G06F11/00

摘要： An example device may include processing circuitry and a management controller. The processing circuitry may include a communications interface that includes a first register and a second register. The first register may include a freshness bit and a number of first data bits. The second register may include a number of second data bits that correspond, respectively, to the first data bits. The processing circuitry may write variously to the first data bits in response to detected events, set the freshness bit in response to the management controller reading the first data bits, and reset the freshness bit if any of the first data bits are written to. The management controller may read the first data bits, perform predetermined processing based thereon, write to the second data bits based on the predetermined processing, and request a register transfer. The processing circuitry may, in response to the management controller requesting the register transfer, transfer values of the second data bits to their respectively corresponding first data bits if and only if the freshness bit is currently asserted.