公开(公告)号：US20250165813A1

公开(公告)日：2025-05-22

申请号：US18518276

申请日：2023-11-22

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Eitan Frachtenberg ,  Sai Rahul Chalamalasetti ,  Izzat El Hajj

IPC: G06N5/022

Abstract: An ML model is trained to learn relationships between empirical distributions of telltale indicators and empirical distributions of variability benchmarks associated with executing an application on a first computer system having a first configuration. At least one empirical distribution of a first variability benchmark associated with the application is specified to the ML model. Output information indicative of at least one telltale indicator that is associated with the first variability benchmark is received from the ML model.

公开(公告)号：US11086660B2

公开(公告)日：2021-08-10

申请号：US16083284

申请日：2016-03-09

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Izzat El Hajj ,  Alexander Merritt ,  Gerd Zellweger ,  Dejan S Milojicic

IPC: G06F9/48 ,  G06F12/10 ,  G06F12/02 ,  G06F12/08

Abstract: Techniques for a thread in client process to switch to a server virtual address space are provided. In one aspect, a process may attach to a server virtual address space. A request may be received from a client thread within the client process to switch from a virtual address space associated with the client thread to a server virtual address space. The client thread may switch from the client thread associated virtual address space to the server virtual address space.

公开(公告)号：US10754792B2

公开(公告)日：2020-08-25

申请号：US15774233

申请日：2016-01-29

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Izzat El Hajj ,  Alexander Merritt ,  Gerd Zellweger ,  Dejan S. Milojicic

IPC: G06F12/109 ,  G06F9/448 ,  G06F12/02

Abstract: Example implementations relate to persistent virtual address spaces. In one example, persistent virtual address spaces can employ a non-transitory processor readable medium including instructions to receive a whole data structure of a virtual address space (VAS) associated with a process, where the whole data structure includes data and metadata of the VAS, and store the data and the metadata of the VAS in a non-volatile memory to form a persistent VAS (PVAS).

公开(公告)号：US10592431B2

公开(公告)日：2020-03-17

申请号：US16101997

申请日：2018-08-13

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Izzat El Hajj ,  Alexander Marshall Merritt ,  Gerd Zellweger ,  Dejan S. Milojicic ,  Paolo Faraboschi

IPC: G06F12/00 ,  G06F12/109 ,  G06F12/1009

Abstract: According to examples, an apparatus may include a processor to address a physical memory having memory sections, in which a first set of memory sections may be shared between processes and a second set of memory sections may be specific to an individual process. The apparatus may also include a shared virtual address space register to provide translation for the first set of memory sections shared between processes and a process virtual address space register to provide translation for the second set of memory sections specific to the individual process. The translation for the second set of memory sections may be independent from the translation for the first set of memory sections.

公开(公告)号：US20200050553A1

公开(公告)日：2020-02-13

申请号：US16101997

申请日：2018-08-13

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Izzat El Hajj ,  Alexander Marshall Merritt ,  Gerd Zellweger ,  Dejan S. Milojicic ,  Paolo Faraboschi

IPC: G06F12/109 ,  G06F12/1009

Abstract: According to examples, an apparatus may include a processor to address a physical memory having memory sections, in which a first set of memory sections may be shared between processes and a second set of memory sections may be specific to an individual process. The apparatus may also include a shared virtual address space register to provide translation for the first set of memory sections shared between processes and a process virtual address space register to provide translation for the second set of memory sections specific to the individual process. The translation for the second set of memory sections may be independent from the translation for the first set of memory sections.

公开(公告)号：US20190095242A1

公开(公告)日：2019-03-28

申请号：US16083284

申请日：2016-03-09

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Izzat El Hajj ,  Alexander Merritt ,  Gerd Zellweger ,  Dejan S Milojicic

IPC: G06F9/48 ,  G06F12/10

Abstract: Techniques for a thread in client process to switch to a server virtual address space are provided. In one aspect, a process may attach to a server virtual address space. A request may be received from a client thread within the client process to switch from a virtual address space associated with the client thread to a server virtual address space. The client thread may switch from the client thread associated virtual address space to the server virtual address space.

公开(公告)号：US20180322067A1

公开(公告)日：2018-11-08

申请号：US15774233

申请日：2016-01-29

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Izzat El Hajj ,  Alexander Merritt ,  Gerd Zellweger ,  Dejan S. Milojicic

IPC: G06F12/109 ,  G06F9/448

Abstract: Example implementations relate to persistent virtual address spaces. In one example, persistent virtual address spaces can employ a non-transitory processor readable medium including instructions to receive a whole data structure of a virtual address space (VAS) associated with a process, where the whole data structure includes data and metadata of the VAS, and store the data and the metadata of the VAS in a non-volatile memory to form a persistent VAS (PVAS).