公开(公告)号：US12061552B2

公开(公告)日：2024-08-13

申请号：US18315806

申请日：2023-05-11

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Michael Malewicki ,  Thomas McGee ,  Michael S. Woodacre

IPC: G06F12/08 ,  G06F12/0808 ,  G06F12/0817 ,  G06F12/084 ,  G06F12/14

CPC classification number: G06F12/0817 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/1441

Abstract: Example implementations relate to cache coherency protocols as applied to a memory block range. Exclusive ownership of a range of blocks of memory in a default shared state may be tracked by a directory. The directory may be associated with a first processor of a set of processors. When a request is received from a second processor of the set of processors to read one or more blocks of memory absent from the directory, one or more blocks may be transmitted in the default shared state to the second processor. The blocks absent from the directory may not be tracked in the directory.

公开(公告)号：US20230281127A1

公开(公告)日：2023-09-07

申请号：US18315806

申请日：2023-05-11

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Michael Malewicki ,  Thomas McGee ,  Michael S. Woodacre

IPC: G06F12/0817 ,  G06F12/14 ,  G06F12/0808 ,  G06F12/084

CPC classification number: G06F12/0817 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/1441

Abstract: Example implementations relate to cache coherency protocols as applied to a memory block range. Exclusive ownership of a range of blocks of memory in a default shared state may be tracked by a directory. The directory may be associated with a first processor of a set of processors. When a request is received from a second processor of the set of processors to read one or more blocks of memory absent from the directory, one or more blocks may be transmitted in the default shared state to the second processor. The blocks absent from the directory may not be tracked in the directory.

公开(公告)号：US20200349076A1

公开(公告)日：2020-11-05

申请号：US16399230

申请日：2019-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Frank R. Dropps ,  Michael S. Woodacre ,  Thomas McGee ,  Michael Malewicki

IPC: G06F12/0817

Abstract: In exemplary aspects of cache coherency management, a first request is received and includes an address of a first memory block in a shared memory. The shared memory includes memory blocks of memory devices associated with respective processors. Each of the memory blocks are associated with one of a plurality of memory categories indicating a protocol for managing cache coherency for the respective memory block. A memory category associated with the first memory block is determined and a response to the first request is based on the memory category of the first memory block. The first memory block and a second memory block are included in one of the same memory devices, and the memory category of the first memory block is different than the memory category of the second memory block.

公开(公告)号：US11687459B2

公开(公告)日：2023-06-27

申请号：US17230286

申请日：2021-04-14

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Michael Malewicki ,  Thomas McGee ,  Michael S. Woodacre

IPC: G06F12/08 ,  G06F12/0817 ,  G06F12/14 ,  G06F12/0808 ,  G06F12/084

CPC classification number: G06F12/0817 ,  G06F12/084 ,  G06F12/0808 ,  G06F12/1441

Abstract: Example implementations relate to cache coherency protocols as applied to a memory block range. Exclusive ownership of a range of blocks of memory in a default shared state may be tracked by a directory. The directory may be associated with a first processor of a set of processors. When a request is received from a second processor of the set of processors to read one or more blocks of memory absent from the directory, one or more blocks may be transmitted in the default shared state to the second processor. The blocks absent from the directory may not be tracked in the directory.

公开(公告)号：US11586541B2

公开(公告)日：2023-02-21

申请号：US16944905

申请日：2020-07-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Derek Schumacher ,  Randy Passint ,  Thomas McGee ,  Michael Malewicki ,  Michael S. Woodacre

IPC: G06F12/08 ,  G06F13/40 ,  G06F12/0815

Abstract: One embodiment can provide a node controller in a multiprocessor system. The node controller can include a processor interface to interface with a processor, a memory interface to interface with a fabric-attached memory, a node-controller interface to interface with a remote node controller, and a cache-coherence logic to operate in a first mode or a second mode. The cache-coherence logic manages cache coherence for a local memory of the processor coupled to the processor interface when operating in the first mode, and the cache-coherence logic manages cache coherence for the fabric-attached memory coupled to the memory interface when operating in the second mode.

公开(公告)号：US20220035742A1

公开(公告)日：2022-02-03

申请号：US16944905

申请日：2020-07-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Derek Schumacher ,  Randy Passint ,  Thomas McGee ,  Michael Malewicki ,  Michael S. Woodacre

IPC: G06F12/0815 ,  G06F13/40

Abstract: One embodiment can provide a node controller in a multiprocessor system. The node controller can include a processor interface to interface with a processor, a memory interface to interface with a fabric-attached memory, a node-controller interface to interface with a remote node controller, and a cache-coherence logic to operate in a first mode or a second mode. The cache-coherence logic manages cache coherence for a local memory of the processor coupled to the processor interface when operating in the first mode, and the cache-coherence logic manages cache coherence for the fabric-attached memory coupled to the memory interface when operating in the second mode.

公开(公告)号：US20200349075A1

公开(公告)日：2020-11-05

申请号：US16399455

申请日：2019-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Thomas McGee ,  Michael S. Woodacre ,  Michael Malewicki

IPC: G06F12/0815

Abstract: In exemplary aspects of enforcing cache coherency, a request is received from a node controller, to process a cache coherent operation on a memory block in a shared memory. Based on the information included in the request, a determination is made as to whether the request was transmitted from a processor that is remote relative to the memory that includes the memory block referenced in the request. If the request is from a remote processor, the hardware-based cache coherency of the system is disabled. Instead, the request is processed according to software-based cache coherency mechanisms. A response to the request is transmitted to the requestor.

公开(公告)号：US11714755B2

公开(公告)日：2023-08-01

申请号：US16944905

申请日：2020-07-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Derek Schumacher ,  Randy Passint ,  Thomas McGee ,  Michael Malewicki ,  Michael S. Woodacre

IPC: G06F12/08 ,  G06F13/40 ,  G06F12/0815

CPC classification number: G06F12/0815 ,  G06F13/4027 ,  G06F2212/1032

Abstract: One embodiment can provide a node controller in a multiprocessor system. The node controller can include a processor interface to interface with a processor, a memory interface to interface with a fabric-attached memory, a node-controller interface to interface with a remote node controller, and a cache-coherence logic to operate in a first mode or a second mode. The cache-coherence logic manages cache coherence for a local memory of the processor coupled to the processor interface when operating in the first mode, and the cache-coherence logic manages cache coherence for the fabric-attached memory coupled to the memory interface when operating in the second mode.

公开(公告)号：US11556471B2

公开(公告)日：2023-01-17

申请号：US16399230

申请日：2019-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Frank R. Dropps ,  Michael S. Woodacre ,  Thomas McGee ,  Michael Malewicki

IPC: G06F12/0817

Abstract: In exemplary aspects of cache coherency management, a first request is received and includes an address of a first memory block in a shared memory. The shared memory includes memory blocks of memory devices associated with respective processors. Each of the memory blocks are associated with one of a plurality of memory categories indicating a protocol for managing cache coherency for the respective memory block. A memory category associated with the first memory block is determined and a response to the first request is based on the memory category of the first memory block. The first memory block and a second memory block are included in one of the same memory devices, and the memory category of the first memory block is different than the memory category of the second memory block.

公开(公告)号：US11314637B2

公开(公告)日：2022-04-26

申请号：US16888123

申请日：2020-05-29

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Frank R. Dropps ,  Thomas McGee ,  Michael Malewicki

IPC: G06F12/02 ,  G06F12/084 ,  G06F9/38 ,  G06F9/54 ,  G06F12/123

Abstract: To reduce latency and bandwidth consumption in systems, systems and methods are provided for grouping multiple cache line request messages in a related and speculative manner. That is, multiple cache lines are likely to have the same state and ownership characteristics, and therefore, requests for multiple cache lines can be grouped. Information received in response can be directed to the requesting processor socket, and those speculatively received (not actually requested, but likely to be requested) can be maintained in queue or other memory until a request is received for that information, or until discarded to free up tracking space for new requests.