公开(公告)号：US20240345857A1

公开(公告)日：2024-10-17

申请号：US18133895

申请日：2023-04-12

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Brian J. Johnson ,  Frank R. Dropps ,  Derek S. Schumacher ,  Thomas Edward McGee

IPC: G06F9/455

CPC classification number: G06F9/45558 ,  G06F2009/45579 ,  G06F2009/45583

Abstract: A first hypervisor running on a first processor cluster is provided. During operation, the first hypervisor can determine a first set of processing nodes and a first memory unit of the first processor cluster in response to the booting up of a first Basic Input/Output System (BIOS) of the first processor cluster. The first hypervisor can discover a second hypervisor running on a second processor cluster comprising a second set of processing nodes and a second memory unit. The first hypervisor can operate, with the second hypervisor, a distributed system comprising the first and second sets of processing nodes and the first and second memory units. The first hypervisor can then operate, with the second hypervisor, a global virtual machine on the distributed system. The virtual memory space of the global virtual machine can be mapped to respective memory spaces of the first and second processor clusters.

公开(公告)号：US12282662B2

公开(公告)日：2025-04-22

申请号：US17898189

申请日：2022-08-29

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Thomas Edward McGee ,  Brian J. Johnson ,  Frank R. Dropps ,  Derek S. Schumacher ,  Stuart C. Haden ,  Michael S. Woodacre

IPC: G06F3/06 ,  G06F12/0817

Abstract: One aspect of the application can provide a system and method for replacing a failing node with a spare node in a non-uniform memory access (NUMA) system. During operation, in response to determining that a node-migration condition is met, the system can initialize a node controller of the spare node such that accesses to a memory local to the spare node are to be processed by the node controller, quiesce the failing node and the spare node to allow state information of processors on the failing node to be migrated to processors on the spare node, and subsequent to unquiescing the failing node and the spare node, migrate data from the failing node to the spare node while maintaining cache coherence in the NUMA system and while the NUMA system remains in operation, thereby facilitating continuous execution of processes previously executed on the failing node.

公开(公告)号：US11188480B1

公开(公告)日：2021-11-30

申请号：US15930263

申请日：2020-05-12

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Frank R. Dropps ,  Thomas Edward McGee

IPC: G06F13/00 ,  G06F12/128 ,  G06F12/123 ,  G06F9/30 ,  G06F12/0815

Abstract: Systems and methods are provided for addressing die are inefficiencies associated with the use of redundant ternary content-addressable memory (TCAM) for facilitating error detection and correction. Only a portion of redundant TCAMs (or portions of the same TCAM) are reserved for modified coherency directory cache entries, while remaining portions are available for unmodified coherency directory cache entries. The amount of space reserved for redundant, modified coherency directory cache entries can be programmable and adaptable.

公开(公告)号：US20240069742A1

公开(公告)日：2024-02-29

申请号：US17898189

申请日：2022-08-29

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Thomas Edward McGee ,  Brian J. Johnson ,  Frank R. Dropps ,  Derek S. Schumacher ,  Stuart C. Haden ,  Michael S. Woodacre

IPC: G06F3/06 ,  G06F12/0817

CPC classification number: G06F3/0617 ,  G06F3/0647 ,  G06F3/0679 ,  G06F12/0828 ,  G06F2212/271 ,  G06F2212/621

Abstract: One aspect of the application can provide a system and method for replacing a failing node with a spare node in a non-uniform memory access (NUMA) system. During operation, in response to determining that a node-migration condition is met, the system can initialize a node controller of the spare node such that accesses to a memory local to the spare node are to be processed by the node controller, quiesce the failing node and the spare node to allow state information of processors on the failing node to be migrated to processors on the spare node, and subsequent to unquiescing the failing node and the spare node, migrate data from the failing node to the spare node while maintaining cache coherence in the NUMA system and while the NUMA system remains in operation, thereby facilitating continuous execution of processes previously executed on the failing node.