公开(公告)号：US20230297505A1

公开(公告)日：2023-09-21

申请号：US17895236

申请日：2022-08-25

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： WONGI HONG ,  CHULHO LEE

IPC分类号： G06F12/0802

CPC分类号： G06F12/0802 ,  G06F2212/271

摘要： A storage device includes; a first memory subsystem including a first nonvolatile memory device (NVM), a first storage controller configured to control operation of the first NVM, and a first resource, and a second memory subsystem including a second NVM, a second storage controller configured to control operation of the second NVM, and a second resource, wherein the first resource is a shared resource useable by the second memory subsystem, and the second resource is shared resource useable by the first memory subsystem.

公开(公告)号：US20180190329A1

公开(公告)日：2018-07-05

申请号：US15394311

申请日：2016-12-29

申请人： SanDisk Technologies LLC

发明人： Gulzar A. Kathawala ,  Sergey Anatolievich Gorobets ,  Kroum S. Stoev ,  Jack Edward Frayer ,  Liam Michael Parker

IPC分类号： G11C7/04 ,  G06F3/06 ,  G06F12/02 ,  G11C11/406 ,  G11C14/00

CPC分类号： G11C7/04 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/202 ,  G06F2212/271 ,  G06F2212/7202

摘要： A system and method is disclosed for managing data in a non-volatile memory. The system may include a non-volatile memory having multiple non-volatile memory sub-drives, including a staging sub-drive to receive all data from a host and a plurality of other sub-drives each associated with a respective data temperature range. A controller of the memory system is configured to route all incoming host data only to the staging sub-drive and during garbage collection each individual piece of valid data from a selected source block in a selected source sub-drive is routed to a respective one of the sub-drives. The method may include only routing host data to the staging sub-drive and only relocating valid data to sub-drives other than the staging sub-drive based on a determined temperature of valid data and a unique temperature range associated with sub-drives other than the staging sub-drive in the non-volatile memory system.

公开(公告)号：US09690706B2

公开(公告)日：2017-06-27

申请号：US14668831

申请日：2015-03-25

申请人： Intel Corporation

发明人： Rahul Pal ,  Ishwar Agarwal ,  Manoj K. Arora

IPC分类号： G06F12/08 ,  G06F12/084

CPC分类号： G06F12/084 ,  G06F2212/2542 ,  G06F2212/271

摘要： Resolving coherency issues inherent in sharing distributed cache is described. A chip multiprocessor may include at least first and second processing clusters, each having multiple cores of a processor, multiple cache slices co-located with the multiple cores, and a memory controller (MC). The processor stores directory information in a memory coupled to the processor to indicate cluster cache ownership of a first address space to the first cluster. In response to a request to change the cluster cache ownership of the first address space, the processor may remap first lines of first cache slices, corresponding to the first address space, to second lines in second cache slices of the second cluster, and update the directory information (e.g., a state of the first cache lines) to change the cluster cache ownership of the first address space to the second cluster. One of the MCs may manage such updating of the directory.

公开(公告)号：US09542315B2

公开(公告)日：2017-01-10

申请号：US13917126

申请日：2013-06-13

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Volker Strumpen ,  Matteo Frigo

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F12/12 ,  G06F3/06

CPC分类号： G06F12/0811 ,  G06F3/0689 ,  G06F12/0897 ,  G06F12/123 ,  G06F2212/271

摘要： A tiled storage array provides reduction in access latency for frequently-accessed values by re-organizing to always move a requested value to a front-most storage element of array. The previous occupant of the front-most location is moved backward according to a systolic pulse, and the new occupant is moved forward according to the systolic pulse, preserving the uniqueness of the stored values within the array, and providing for multiple in-flight access requests within the array. The placement heuristic that moves the values according to the systolic pulse can be implemented by control logic within identical tiles, so that the placement heuristic moves the values according to the position of the tiles within the array. The movement of the values can be performed via only next-neighbor connections of adjacent tiles within the array.

摘要翻译： 平铺的存储阵列通过重新组织来提供频繁访问值的访问延迟，从而始终将请求的值移动到阵列的最前面的存储元素。 根据收缩期脉搏，最前面的位置的前乘客向后移动，并且新乘员根据收缩脉冲向前移动，保持阵列内存储值的唯一性，并提供多个飞行中访问 数组内的请求。 根据收缩期脉冲移动值的放置启发式可以由相同瓦片内的控制逻辑实现，使得放置启发式根据阵列内的瓦片的位置来移动值。 值的移动可以仅通过阵列内的相邻瓦片的下一个相邻连接来执行。

公开(公告)号：US20160357683A1

公开(公告)日：2016-12-08

申请号：US15243196

申请日：2016-08-22

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Susumu TAKEDA ,  Shinobu FUJITA

IPC分类号： G06F12/0895 ,  G06F12/1009 ,  G06F12/1045 ,  G06F12/0897

CPC分类号： G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1045 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/271 ,  G06F2212/507

摘要： A cache memory system includes cache memories of at least one layer, at least one of the cache memories having a data cache to store data and a tag to store an address of data stored in the data cache, and a first address conversion information storage to store entry information that includes address conversion information for virtual addresses issued by a processor to physical addresses and cache presence information that indicates whether data corresponding to the converted physical address is stored in a specific cache memory of at least one layer among the cache memories,

摘要翻译： 高速缓冲存储器系统包括至少一层的高速缓存存储器，高速缓存存储器中的至少一个具有存储数据的数据高速缓存和用于存储存储在数据高速缓存中的数据的地址的标签，以及第一地址转换信息存储器 将包括处理器发出的虚拟地址的地址转换信息存储到物理地址的存储条目信息和指示与转换的物理地址相对应的数据是否存储在高速缓冲存储器中的至少一层的特定高速缓冲存储器中的高速缓存存在信息，

公开(公告)号：US20160124854A1

公开(公告)日：2016-05-05

申请号：US14533579

申请日：2014-11-05

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Ekaterina M. Ambroladze ,  Garrett M. Drapala ,  Norbert Hagspiel ,  Sascha Junghans ,  Matthias Klein ,  Gary E. Strait

IPC分类号： G06F12/08 ,  G06F13/42

CPC分类号： G06F3/0604 ,  G06F3/061 ,  G06F3/0647 ,  G06F3/0659 ,  G06F3/0683 ,  G06F12/0842 ,  G06F13/4221 ,  G06F2212/271 ,  G06F2212/604

摘要： A method, computer program product, and system for maintaining a proper ordering of a data steam that includes two or more sequentially ordered stores, the data stream being moved to a destination memory device, the two or more sequentially ordered stores including at least a first store and a second store, wherein the first store is rejected by the destination memory device. A computer-implemented method includes sending the first store to the destination memory device. A conditional request is sent to the destination memory device for approval to send the second store to the destination memory device, the conditional request dependent upon successful completion of the first store. The second store is cancelled responsive to receiving a reject response corresponding to the first store.

摘要翻译： 一种方法，计算机程序产品和系统，用于维持包括两个或多个顺序排列的存储器的数据流的正确排序，所述数据流被移动到目的地存储器设备，所述两个或多个顺序排序的存储器至少包括第一 存储和第二存储，其中第一存储被目的地存储设备拒绝。 计算机实现的方法包括将第一存储发送到目的地存储设备。 将条件请求发送到目的地存储器设备以批准将第二存储发送到目的地存储器设备，该条件请求取决于第一存储器的成功完成。 响应于接收到对应于第一商店的拒绝响应，第二商店被取消。

公开(公告)号：US08843705B2

公开(公告)日：2014-09-23

申请号：US13572916

申请日：2012-08-13

申请人： Jian Li ,  Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

发明人： Jian Li ,  Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

IPC分类号： G06F12/08

CPC分类号： G06F12/0848 ,  G06F2212/271 ,  Y02D10/13

摘要： A mechanism is provided in a cache for providing a read and write aware cache. The mechanism partitions a large cache into a read-often region and a write-often region. The mechanism considers read/write frequency in a non-uniform cache architecture replacement policy. A frequently written cache line is placed in one of the farther banks. A frequently read cache line is placed in one of the closer banks. The size ratio between read-often and write-often regions may be static or dynamic. The boundary between the read-often region and the write-often region may be distinct or fuzzy.

摘要翻译： 在缓存中提供了一种机制，用于提供读写感知高速缓存。 该机制将大型缓存分区分为常读区域和经常写区域。 该机制将读/写频率视为非均匀缓存架构替换策略。 经常写入的高速缓存行放置在更远的存储区之一中。 经常读取的高速缓存行被放置在其中一个较近的存储体中。 常读区域和经常写区域之间的大小比可以是静态的或动态的。 经常读区域和经常写区域之间的边界可能是不同的或模糊的。

公开(公告)号：US08473723B2

公开(公告)日：2013-06-25

申请号：US12635544

申请日：2009-12-10

申请人： Hillery C Hunter ,  Ronald P Luijten ,  Phillip Stanley-Marbell

发明人： Hillery C Hunter ,  Ronald P Luijten ,  Phillip Stanley-Marbell

IPC分类号： G06F9/48

CPC分类号： G06F9/4856 ,  G06F9/5033 ,  G06F2212/271

摘要： A computer-implemented method for a computerized system having at least a first processor and a second processor, where each of the processors are operatively interconnected to a memory storing a set of data to be processed by a processor. The method includes monitoring data accessed by the first processor while executing, and if the second processor is at a shorter distance than the first processor from the monitored data, instructing to interrupt execution at the first processor and resume the execution at the second processor.

摘要翻译： 一种用于具有至少第一处理器和第二处理器的计算机化系统的计算机实现的方法，其中每个处理器可操作地互连到存储要由处理器处理的一组数据的存储器。 该方法包括在执行时监视由第一处理器访问的数据，并且如果第二处理器距离所监视的数据处于比第一处理器更短的距离，则指示中断第一处理器处的执行并在第二处理器恢复执行。

公开(公告)号：US20100299482A1

公开(公告)日：2010-11-25

申请号：US12470639

申请日：2009-05-22

申请人： Gideon N. Levinsky ,  Paul Caprioli ,  Sherman H. Yip

发明人： Gideon N. Levinsky ,  Paul Caprioli ,  Sherman H. Yip

IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F12/10

CPC分类号： G06F12/0864 ,  G06F12/1027 ,  G06F2212/271

摘要： A method for determining whether to store binary information in a fast way or a slow way of a cache is disclosed. The method includes receiving a block of binary information to be stored in a cache memory having a plurality of ways. The plurality of ways includes a first subset of ways and a second subset of ways, wherein a cache access by a first execution core from one of the first subset of ways has a lower latency time than a cache access from one of the second subset of ways. The method further includes determining, based on a predetermined access latency and one or more parameters associated with the block of binary information, whether to store the block of binary information into one of the first set of ways or one of the second set of ways.

摘要翻译： 公开了一种用于以快速方式或缓存方式存储二进制信息的方法。 该方法包括接收要存储在具有多个方式的高速缓冲存储器中的二进制信息块。 多种方式包括方法的第一子集和方法的第二子集，其中来自第一方法子集之一的第一执行核心的高速缓存访​​问具有比来自第二子集的第二子集 方法。 该方法还包括基于预定访问等待时间和与二进制信息块相关联的一个或多个参数确定是否将二进制信息块存储为第一组方式之一或第二组路径之一。

公开(公告)号：US20100122100A1

公开(公告)日：2010-05-13

申请号：US12640451

申请日：2009-12-17

申请人： Volker Strumper

发明人： Volker Strumper

IPC分类号： G06F1/32 ,  G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/123 ,  G06F2212/1028 ,  G06F2212/271 ,  G06F2212/601 ,  Y02D10/13

摘要： A tiled memory and a method of power management within the tiled memory provides efficient use of energy within a computer storage, which may be a spiral cache memory. The tiled memory is power-managed by placing tiles in a power-saving state, which may be a state in which storage circuits are powered-down and network circuits are powered-up, so that for serially-connected tiles, information can still be forwarded by a tile in the power-saving state. The tiles may be power managed under direction of a central controlled, which sends commands to the tiles to enter and leave the power-saving state, or the tiles may self-manage their power-saving state according to activity measured at the individual tiles. Activity may be measured at the tiles of a spiral cache by comparing a hit rate and a push back rate to corresponding thresholds. The measurements may be used with either tile-managed or centrally-managed techniques.

摘要翻译： 平铺存储器和平铺内存中的电源管理方法提供计算机存储器内的能量的有效利用，计算机存储器可以是螺旋高速缓冲存储器。 平铺存储器是通过将瓦片放置在省电状态来进行功率管理的，这可能是存储电路掉电和网络电路通电的状态，因此对于串行连接的瓦片，信息仍然可以 在省电状态下由瓦片转发。 瓦片可以在中央控制的方向下进行功率管理，其向瓦片发送命令以进入和离开省电状态，或者瓦片可以根据在各个瓦片处测量的活动来自我管理其省电状态。 可以通过将命中率和推回速率与对应的阈值进行比较来在螺旋高速缓存的瓦片处测量活动。 测量可以与瓦片管理的或集中管理的技术一起使用。