公开(公告)号：US11276645B2

公开(公告)日：2022-03-15

申请号：US16997003

申请日：2020-08-19

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Nan Zhao ,  Wenxu Xie ,  Junlei Tao ,  Shanghsuan Chiang ,  HuiLi Fu

IPC: H01L23/12 ,  H01L23/34 ,  H01L23/48 ,  H01L21/00 ,  H01L21/44 ,  H05K7/20 ,  H05K1/00 ,  H05K7/00 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00

Abstract: A chip and a packaging method thereof. In the chip, first solder pads in a first solder pad array on a first substrate are attached to corresponding second pins in second pin arrays on different dies to implement short-distance and high-density interconnection of the different dies. A molding body is used to wrap a first pin, a second pin, a first solder pad, and the first substrate, so that a fan-out unit and the first substrate are molded into an integral structure. In the integral structure, bottoms of first pins that are in a first pin array on a die and that are electrically connected to a periphery of the chip are not wrapped by the molding body.