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公开(公告)号：US10542581B2
公开(公告)日：2020-01-21
申请号：US15634644
申请日：2017-06-27
Applicant: Huawei Technologies Co., Ltd.
Inventor： Zishuai Li , Zhulin Cheng , Nan Zhao
Abstract: The present invention relates to a technology for managing discontinuous reception (DRX). DRX cycles of different cycle lengths are configured according to service types of UE. If it is identified that the user equipment (UE) initiates a voice service, a relatively short first long DRX cycle is configured for the UE or the UE is instructed to deactivate DRX; and if it is identified that the UE does not perform a voice service, a relatively long second long DRX cycle is configured for the UE. The UE performs corresponding receiver on/off control according to the configured long DRX cycle, so as to receive downlink data or hibernate. According to the solution provided in the present invention, a DRX cycle of UE can be flexibly configured, so that a better balance between power consumption reduction of the UE and user experience improvement can be achieved.
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公开(公告)号：US12266617B2
公开(公告)日：2025-04-01
申请号：US17746186
申请日：2022-05-17
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Nan Zhao , Chunghsuan Tsai , Shanghsuan Chiang
IPC: H01L23/00 , H01L21/56 , H01L23/31 , H01L23/538 , H01L25/065
Abstract: A chip package includes a substrate, a first die, a second die, and a beam structure. The first die and the second die are disposed on a side of the substrate and are electrically connected to the substrate. The beam structure is disposed between the first die and the second die. A first end of the beam structure is stacked with and fixedly connected to a part of the first die, a second end is stacked with and fixedly connected to a part of the second die, and the beam structure is insulated from and connected to the first die and the second die. A thermal expansion coefficient of the beam structure is less than a thermal expansion coefficient of the substrate.
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公开(公告)号：US11276645B2
公开(公告)日：2022-03-15
申请号：US16997003
申请日：2020-08-19
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Nan Zhao , Wenxu Xie , Junlei Tao , Shanghsuan Chiang , HuiLi Fu
IPC: H01L23/12 , H01L23/34 , H01L23/48 , H01L21/00 , H01L21/44 , H05K7/20 , H05K1/00 , H05K7/00 , H01L23/538 , H01L21/48 , H01L21/56 , H01L23/31 , H01L23/367 , H01L23/00 , H01L23/498 , H01L25/00
Abstract: A chip and a packaging method thereof. In the chip, first solder pads in a first solder pad array on a first substrate are attached to corresponding second pins in second pin arrays on different dies to implement short-distance and high-density interconnection of the different dies. A molding body is used to wrap a first pin, a second pin, a first solder pad, and the first substrate, so that a fan-out unit and the first substrate are molded into an integral structure. In the integral structure, bottoms of first pins that are in a first pin array on a die and that are electrically connected to a periphery of the chip are not wrapped by the molding body.
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公开(公告)号：US20180308789A1
公开(公告)日：2018-10-25
申请号：US16023181
申请日：2018-06-29
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Nan Zhao , Wenxu Xie , Xiaodong Zhang , HuiLi Fu
IPC: H01L23/485 , H01L23/49 , H01L23/00 , H01L21/56 , H01L23/367
CPC classification number: H01L23/485 , H01L21/563 , H01L23/3672 , H01L23/49 , H01L24/16 , H01L24/81 , H01L24/83 , H01L24/96 , H01L2224/12105 , H01L2224/1403 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/73267 , H01L2924/15159 , H01L2924/15192 , H01L2924/15311 , H01L2924/16251 , H01L2924/3025
Abstract: The invention discloses a packaging structure, including a substrate, a fan-out unit, and a wiring layer. The fan-out unit includes a first chip and a second chip. The first chip includes a first pin array, and the second chip includes a second pin array. The fan-out unit further includes a third pin array. The first pin array, the second pin array, and the third pin array are all disposed facing the substrate. The wiring layer bridges over between the first pin array and the second pin array, and is configured to connect each first pin in the first pin array to a corresponding second pin in the second pin array. The substrate is provided with a soldering pad that is electrically connected to a wiring layer in the substrate, and the third pin array is connected to the soldering pad.
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公开(公告)号：US20170295608A1
公开(公告)日：2017-10-12
申请号：US15634644
申请日：2017-06-27
Applicant: Huawei Technologies Co., Ltd.
Inventor： Zishuai Li , Zhulin Cheng , Nan Zhao
Abstract: The present invention relates to a technology for managing discontinuous reception (DRX). DRX cycles of different cycle lengths are configured according to service types of UE. If it is identified that the user equipment (UE) initiates a voice service, a relatively short first long DRX cycle is configured for the UE or the UE is instructed to deactivate DRX; and if it is identified that the UE does not perform a voice service, a relatively long second long DRX cycle is configured for the UE. The UE performs corresponding receiver on/off control according to the configured long DRX cycle, so as to receive downlink data or hibernate. According to the solution provided in the present invention, a DRX cycle of UE can be flexibly configured, so that a better balance between power consumption reduction of the UE and user experience improvement can be achieved.
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Patent Agency Ranking
公开(公告)号：US20130221537A1
公开(公告)日：2013-08-29
申请号：US13754515
申请日：2013-01-30
Applicant: Huawei Technologies Co., Ltd.
Inventor： HuiLi Fu , Ting Lei , Xiaowei Wang , Nan Zhao
IPC: H01L23/498
CPC classification number: H01L23/49827 , H01L23/147 , H01L23/49816 , H01L23/50 , H01L25/0657 , H01L2224/16 , H01L2224/48091 , H01L2225/06513 , H01L2225/06541 , H01L2924/30107 , H01L2924/00014 , H01L2924/00
Abstract: A semiconductor device is provided in the present invention. The semiconductor device includes a silicon substrate, configured to bear a chip; a power management module arranged inside the silicon substrate, configured to convert a power supply voltage to an input voltage required by the chip; and an interconnecting system, configured to receive the power supply voltage, transmit the power supply voltage to the power management module, and transmit the input voltage to the chip. With the semiconductor device according to the embodiments of the present invention, the power supply voltage can be directly sent from the silicon substrate to the chip after being generated, thereby shortening the power supply link and reducing the power supply/ground noise.
Abstract translation: 在本发明中提供半导体器件。 半导体器件包括被配置为承载芯片的硅衬底; 布置在所述硅衬底内的电源管理模块，被配置为将电源电压转换为所述芯片所需的输入电压; 以及互连系统，被配置为接收电源电压，将电源电压发送到电源管理模块，并将输入电压传送到芯片。 利用根据本发明的实施例的半导体器件，可以在生成之后将电源电压从硅衬底直接发送到芯片，从而缩短电源链路并降低电源/接地噪声。
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公开(公告)号：US10141250B2
公开(公告)日：2018-11-27
申请号：US14980484
申请日：2015-12-28
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yuchen Xin , Nan Zhao , Chen Wang
IPC: H01L23/00 , H01L23/498 , H01L23/538 , H05K1/18
Abstract: A chip includes a substrate and a die that are wrapped together by means of a packaging process. Multiple substrate cables corresponding to attachment points are laid out in the substrate. Solder joints in a solder joint matrix at a bottom of the substrate include a first solder joint group and a second solder joint group that are arranged along two parallel lines. Substrate cables connected to solder joints in the first solder joint group have an equal length. Substrate cables connected to solder joints in the second solder joint group have an equal length.
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公开(公告)号：US09681549B2
公开(公告)日：2017-06-13
申请号：US15261389
申请日：2016-09-09
Applicant: Huawei Technologies Co., Ltd.
Inventor： Tewei Chen , Huili Fu , Nan Zhao
CPC classification number: H05K1/181 , H01F5/00 , H01F19/00 , H01F27/292 , H01F2005/006 , H05K3/3426 , H05K2201/1003 , H05K2201/10121 , H05K2201/10757 , Y02P70/613
Abstract: A conical inductor provided in the present invention includes: a housing, a conical coil located inside the housing, a first pin and a second pin respectively connected to two ends of the conical coil, where one end of the first pin is connected to one end of the conical coil, the other end of the first pin is connected to a hole in a first side wall of the housing in a fastened manner, one end of the second pin is connected to the other end of the conical inductor, and the other end of the second pin is connected to a hole in a second side wall of the housing in a fastened manner; and each of the first pin and the second pin includes one segment of waveform segment fluctuating in a direction perpendicular to a top wall of the housing.
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公开(公告)号：US20160197051A1
公开(公告)日：2016-07-07
申请号：US14980484
申请日：2015-12-28
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yuchen Xin , Nan Zhao , Chen Wang
IPC: H01L23/00 , H01L23/498 , H05K1/18
CPC classification number: H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/5381 , H01L23/5386 , H01L24/13 , H01L24/16 , H01L2224/131 , H01L2224/16227 , H01L2224/81191 , H01L2924/15311 , H05K1/181 , H01L2924/014
Abstract: A chip includes a substrate and a die that are wrapped together by means of a packaging process. Multiple substrate cables corresponding to attachment points are laid out in the substrate. Solder joints in a solder joint matrix at a bottom of the substrate include a first solder joint group and a second solder joint group that are arranged along two parallel lines. Substrate cables connected to solder joints in the first solder joint group have an equal length. Substrate cables connected to solder joints in the second solder joint group have an equal length.
Abstract translation: 芯片包括通过包装工艺包裹在一起的基底和模具。 对应于附接点的多个基板电缆布置在基板中。 在基板的底部的焊点基体中的焊接点包括沿着两条平行线布置的第一焊点组和第二焊点组。 与第一焊接组中的焊点相连的基板电缆具有相等的长度。 连接到第二焊接组中的焊点的基板电缆具有相等的长度。
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公开(公告)号：US20240373346A1
公开(公告)日：2024-11-07
申请号：US18776852
申请日：2024-07-18
Applicant: Huawei Technologies Co., Ltd.
Inventor： Xiaowen Li , Xinli Geng , Nan Zhao , Xiaowen Li
Abstract: A base station energy saving method includes: determining, for one or more low-energy-efficiency cells in a low-energy-efficiency cell set, a high-energy-efficiency cell paired with each low-energy-efficiency cell from a high-energy-efficiency cell set, where a coverage area of the low-energy-efficiency cell partially overlaps a coverage area of the high-energy-efficiency cell paired with the low-energy-efficiency cell, and energy efficiency of a cell in the low-energy-efficiency cell set is lower than energy efficiency of a cell in the high-energy-efficiency cell set; and sending indication information to a base station of the low-energy-efficiency cell or a management network element configured to manage the low-energy-efficiency cell. The user equipment in the low-energy-efficiency cell may be handed over to the high-energy-efficiency cell paired with the low-energy-efficiency cell.
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