Amplifier, Amplification Circuit And Phase Shifter

    公开(公告)号:US20210013850A1

    公开(公告)日:2021-01-14

    申请号:US17037224

    申请日:2020-09-29

    Abstract: Amplifiers, amplification circuits, and phase shifters, for example, for flexibly adjusting an output phase to thereby meet a requirement of a constant phase on a link in a communications field, are provided. In one aspect, an amplifier includes first, second, and third MOS transistors. The first MOS transistor includes a gate separately coupled to a signal input end and a bias voltage input end, a source coupled to a power supply, and a drain separately coupled to sources of the second and third MOS transistors. A drain of the third MOS transistor is coupled to a ground, and a drain of the second MOS transistor is coupled to a signal output end. The bias voltage input end is configured to receive a bias voltage to adjust a phase difference between an input signal at the signal input end and an output signal at the signal output end.

    Variable Gain Amplifier And Phased Array Transceiver

    公开(公告)号:US20220021363A1

    公开(公告)日:2022-01-20

    申请号:US17490900

    申请日:2021-09-30

    Abstract: This application provides a variable gain amplifier and a phased array transceiver, to enable the variable gain amplifier to keep a phase constant when switching a gain, and to enable a gain step to be stable with a frequency. The variable gain amplifier includes an amplification circuit, configured to amplify an input signal; a control circuit, configured to control a gain of the amplification circuit by adjusting an output current of the amplification circuit; and an inductive load and an inductive adjustment circuit, where the inductive load is coupled to a signal output end of the amplification circuit, the inductive adjustment circuit and the inductive load are inductively coupled, and the inductive adjustment circuit is adjustable.

    MULTI-BAND PHASED ARRAY AND ELECTRONIC DEVICE

    公开(公告)号:US20230238701A1

    公开(公告)日:2023-07-27

    申请号:US18193366

    申请日:2023-03-30

    Abstract: Example multi-band phased array are described. One example multi-band phased array includes a plurality of branches coupled to a plurality of multi-band antennas. Each of the plurality of branches includes a low noise amplifier and a power amplifier. The power amplifier and the low noise amplifier are configured to transmit and receive, in a time-sharing manner, a signal of a first frequency band and a signal of a second frequency band that are received by the multi-band phased array, and the first frequency band and the second frequency band are different and do not overlap. Each of the plurality of branches further includes a phase shifter, where the phase shifter is configured to perform phase shifting on the signal of the first frequency band, and the phase shifter is further configured to perform phase shifting on the signal of the second frequency band.

    ELECTRONIC DEVICE AND COMMUNICATION SYSTEM

    公开(公告)号:US20250070816A1

    公开(公告)日:2025-02-27

    申请号:US18941454

    申请日:2024-11-08

    Abstract: The present disclosure relates to electronic devices and communication systems. One example electronic device includes a power divider array that includes a general input port and a plurality of branch output ports. The power divider array has a filter mode and a power splitter mode that are switchable. In the power splitter mode, the power divider array is configured to implement power distribution of a signal from the general input port to the plurality of branch output ports. In the filter mode, the power divider array is configured to filter a signal transmitted between the general input port and the plurality of branch output ports.

    MULTI-CHIP APPARATUS AND ELECTRONIC DEVICE
    5.
    发明公开

    公开(公告)号:US20240014843A1

    公开(公告)日:2024-01-11

    申请号:US18471735

    申请日:2023-09-21

    CPC classification number: H04B1/403 H04B1/0028

    Abstract: The present disclosure relates to multi-chip apparatuses and electronic devices. One example multi-chip apparatus includes a first chip with a first internal signal generator and a first frequency multiplier, and a second chip with a second internal signal generator and a second frequency multiplier. The second frequency multiplier includes a first receiving circuit, a second receiving circuit, and a load circuit, where an input end of the first receiving circuit is coupled to an output end of the first internal signal generator, an input end of the second receiving circuit is coupled to an output end of the second internal signal generator, and an output end of the first receiving circuit and an output end of the second receiving circuit are coupled to an input end of the load circuit.

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