Abstract:
Systems and methods for improved Variable Speed Drives having active inverters include an input filter for filtering common mode and differential mode currents. A three-phase inductor has three windings, each winding of the three-phase inductor having a center tap dividing each winding into a pair of inductor sections; and a three-phase input capacitor bank connected in a wye configuration to the three center taps at one end, and to a common point at the opposite end. The three-phase input capacitor bank provides a short circuit for frequencies above a predetermined fundamental frequency for shunting such frequencies through the three phase capacitor bank, while passing the predetermined fundamental frequency to an input AC power source.
Abstract:
Systems and methods for operating a variable speed drive to receive an input AC power at a fixed AC input voltage and frequency and provide an output AC power at a variable voltage and variable frequency. The variable speed drive includes a converter stage to convert the input AC voltage to a boosted DC voltage, a DC link connected to the converter stage to filter and store the boosted DC voltage from the converter stage; and an inverter stage to convert the boosted DC voltage into AC power with variable voltage and the variable frequency. An integral bypass contactor is connected in parallel with the VSD between the AC power source and the AC output power. The integral bypass contactor is arranged to bypass the VSD when the VSD output frequency and voltage are approximately equal with the AC input voltage and frequency.
Abstract:
Systems and methods for synchronous operation of variable speed drives having active converters include extending the synchronous operation of an active converter to the AC mains voltage during complete line dropout. A phase angle control circuit includes a squaring amplifier, a first phase-lock loop circuit associated and a second phase-lock loop circuit. The squaring amplifier receives the AC power source and outputs a rectangular output signal to a pair of phase lock loop (PLL) circuits. The first PLL circuit with a first lag-lead filter is configured with a high cutoff frequency to provide the converter stage with a phase angle parameter; and the second phase-lock loop circuit including a second lag-lead filter configured to have a low cutoff frequency to provide the lag-lead filter the capability of storing the phase angle of the mains voltage during mains interruption.