公开(公告)号：US20120000542A1

公开(公告)日：2012-01-05

申请号：US13173409

申请日：2011-06-30

申请人： Hideo ETO ,  Makoto SAITO ,  Nobuyasu NISHIYAMA

发明人： Hideo ETO ,  Makoto SAITO ,  Nobuyasu NISHIYAMA

IPC分类号： F15D1/00 ,  H01L21/306

CPC分类号： G05D7/0623 ,  Y10T137/0368 ,  Y10T137/7759 ,  Y10T137/7761 ,  Y10T137/87314 ,  Y10T137/87322

摘要： According to one embodiment, a flow rate adjusting unit is disposed on a gas passageway and includes a valve that adjusts the flow rate of a gas and an actuator that controls the displacement amount of the valve. A displacement amount storage unit stores displacement amount information in which a displacement amount of the valve, used when a gas flows into the gas passageway at a flow rate defined according to a process procedure before performing the process procedure, is obtained in advance for each process procedure. A setting circuit acquires the displacement amount corresponding to the process procedure from the displacement amount storage unit, and controls the actuator on the basis of the acquired displacement amount.

摘要翻译： 根据一个实施例，流量调节单元设置在气体通道上，并且包括调节气体流量的阀和控制阀的位移量的致动器。 位移量存储单元存储位移量信息，其中，在每个处理预先获得在气体流入气体通道期间使用的阀的位移量以根据处理过程之前的处理程序限定的流量的位移量信息 程序。 设置电路从位移量存储单元获取与处理过程对应的位移量，并基于获取的位移量来控制致动器。

公开(公告)号：US20100203728A1

公开(公告)日：2010-08-12

申请号：US12767842

申请日：2010-04-27

申请人： Nobuyasu NISHIYAMA

发明人： Nobuyasu NISHIYAMA

IPC分类号： H01L21/302

CPC分类号： H01L27/105 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/112 ,  H01L27/11286 ,  H01L27/115 ,  H01L27/11524

摘要： A semiconductor device includes at least two adjacent memory cell blocks, each of the memory cell blocks having a plurality of memory cell units, each of memory cell units having a plurality of electrically reprogrammable and erasable memory cells connected in series, a plurality of cell gates for selecting the plurality of memory cells within the two adjacent memory cell blocks, each of the plurality of cell gates being formed with roughly rectangular closed loops or roughly U shaped open loops, each of the loops being connected to a corresponding cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within one of the two adjacent memory cell blocks and being connected to a corresponding memory cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within the other memory cell block of the two adjacent memory cell blocks and a plurality of pairs of first and second selection gates for selecting the memory cell block, the plurality of cell gates being located between one pair of the first and second selection gates within a corresponding block of the memory cell block.

摘要翻译： 半导体器件包括至少两个相邻的存储器单元块，每个存储器单元块具有多个存储单元单元，每个存储单元单元具有串联连接的多个电可重新编程和可擦除存储单元，多个单元门 为了选择两个相邻的存储单元块内的多个存储器单元，多个单元栅极中的每一个形成有大致矩形的闭环或大致U形的开环，每个循环连接到存储单元的相应单元 在两个相邻存储单元块之一内的多个存储单元单元的相应存储单元单元中，并连接到另一个存储单元块内的多个存储单元单元的相应存储单元单元中的存储单元的对应存储单元 两个相邻的存储单元块的存储单元块和用于选择th的多对第一和第二选择门 e个存储器单元块，所述多个单元栅极位于所述存储单元块的对应块内的一对第一和第二选择栅极之间。

公开(公告)号：US20100027338A1

公开(公告)日：2010-02-04

申请号：US12574438

申请日：2009-10-06

申请人： Nobuyasu NISHIYAMA

发明人： Nobuyasu NISHIYAMA

IPC分类号： G11C16/04 ,  G11C8/00

CPC分类号： H01L27/105 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/112 ,  H01L27/11286 ,  H01L27/115 ,  H01L27/11524

摘要： A semiconductor device includes at least two adjacent memory cell blocks, each of the memory cell blocks having a plurality of memory cell units, each of memory cell units having a plurality of electrically reprogrammable and erasable memory cells connected in series, a plurality of cell gates for selecting the plurality of memory cells within the two adjacent memory cell blocks, each of the plurality of cell gates being formed with roughly rectangular closed loops or roughly U shaped open loops, each of the loops being connected to a corresponding cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within one of the two adjacent memory cell blocks and being connected to a corresponding memory cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within the other memory cell block of the two adjacent memory cell blocks and a plurality of pairs of first and second selection gates for selecting the memory cell block, the plurality of cell gates being located between one pair of the first and second selection gates within a corresponding block of the memory cell block.