公开(公告)号：US20040227160A1

公开(公告)日：2004-11-18

申请号：US10845290

申请日：2004-05-12

申请人： Hitachi, Ltd. ,  Trecenti Technologies, Inc.

发明人： Shingo Nasu ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Yukihiro Kumagai ,  Shuji Ikeda

IPC分类号： H01L027/10

CPC分类号： H01L29/167 ,  H01L21/2807 ,  H01L29/1004 ,  H01L29/1054 ,  H01L29/4966 ,  H01L29/7378

摘要： In semiconductor devices, a semiconductor device is provided which is high in reliability while suppressing changes in characteristics such as threshold voltages. In a semiconductor device which has a gate dielectric film above a semiconductor substrate and also has above the gate dielectric film a gate electrode film made of silicon germanium chosen as its main constituent material, or alternatively in a semiconductor device which has beneath the gate dielectric film a channel made of silicon as its main constituent material and which has below the channel a channel underlayer film made of silicon germanium as its main constituent material, a specifically chosen dopant, such as cobalt (Co) or carbon (C) or nitrogen (N), is added to the gate electrode and the channel underlayer film, for use as the unit for suppressing diffusion of germanium in the gate electrode or in the channel underlayer film.

摘要翻译： 在半导体器件中，提供了一种在抑制诸如阈值电压的特性变化的同时高可靠性的半导体器件。 在半导体器件中，在半导体衬底上方具有栅极电介质膜，并且还具有栅极电介质膜上方的由选择为主要构成材料的硅锗制成的栅电极膜，或者替代地在栅极电介质膜下方的半导体器件 由硅作为其主要构成材料的通道，并且在通道下方具有由硅锗作为其主要构成材料的沟道下层膜，特别选择的掺杂剂，例如钴（Co）或碳（C）或氮（N ）添加到栅极电极和沟道下层膜中，用作抑制栅极电极或沟道下层膜中锗扩散的单元。

公开(公告)号：US20030071313A1

公开(公告)日：2003-04-17

申请号：US10303024

申请日：2002-11-25

申请人： Hitachi, Ltd.

发明人： Koichiro Ishibashi ,  Shuji Ikeda ,  Harumi Wakimoto ,  Kenichi Kuroda

IPC分类号： H01L021/8238 ,  H01L029/94 ,  H01L031/062

CPC分类号： H01L27/092

摘要： The metal layers embedded into the contact holes of various kinds in shape are used as the lines and are employed as the lines for controlling the substrate bias. The first-layer metal line layers are made thin so as to be also employed as the lines for controlling the substrate bias. Moreover, the second-layer metal line layers are employed as the copper line layers. Thereby, a semiconductor integrated circuit which allows a high-speed and low-power operation is provided with a small area and without increasing the number of the masks.

摘要翻译： 嵌入到各种形状的接触孔中的金属层用作线，并且用作用于控制衬底偏压的线。 使第一层金属线层薄，从而也用作用于控制衬底偏压的线。 此外，第二层金属线层用作铜线层。 因此，允许高速和低功率操作的半导体集成电路具有小面积并且不增加掩模的数量。

公开(公告)号：US20020187596A1

公开(公告)日：2002-12-12

申请号：US10162573

申请日：2002-06-06

申请人： Hitachi, Ltd.

发明人： Toshiaki Yamanaka ,  Akio Nishida ,  Yasuko Yoshida ,  Shuji Ikeda ,  Kenichi Kuroda ,  Shiro Kamohara ,  Shinichiro Kimura ,  Eiichi Murakami ,  Hideyuki Matsuoka ,  Masataka Minami

IPC分类号： H01L021/336

CPC分类号： H01L21/823807 ,  H01L21/2652 ,  H01L21/823842 ,  H01L21/823892

摘要： A low threshold voltage NMIS area and a high threshold voltage PMIS area are set by a photoresist mask also used for well formation. Using a photoresist mask with openings for the NMIS and PMIS, the NMIS and PMIS areas are set by one ion implantation step. After gate oxidation, ion implantation is conducted through an amorphous silicon film onto wells, channels, and gate electrodes. A plurality of CMIS threshold voltages can be set and the gate electrodes of both polarities can be formed in a reduced number of steps using photoresist. This solves the problem in which photomasks are required as many as there are ion implantation types for wells, channel stoppers, gate electrodes, and threshold voltage control and hence the number of manufacturing steps and the production cost are increased.

摘要翻译： 低阈值电压NMIS区域和高阈值电压PMIS区域由也用于阱形成的光致抗蚀剂掩模设置。 使用具有用于NMIS和PMIS的开口的光致抗蚀剂掩模，通过一个离子注入步骤设置NMIS和PMIS区域。 栅极氧化后，离子注入通过非晶硅膜导入孔，通道和栅电极。 可以设置多个CMIS阈值电压，并且可以以减少数量的步骤使用光致抗蚀剂形成两个极性的栅电极。 这解决了需要光掩模的问题，因为存在孔，通道阻挡件，栅电极和阈值电压控制的离子注入类型，因此制造步骤的数量和生产成本增加。

公开(公告)号：US20030197213A1

公开(公告)日：2003-10-23

申请号：US10442156

申请日：2003-05-21

申请人： Hitachi, Ltd.

发明人： Koichiro Ishibashi ,  Shuji Ikeda ,  Harumi Wakimoto ,  Kenichi Kuroda

IPC分类号： H01L027/108 ,  H01L029/76 ,  H01L029/94 ,  H01L031/119

CPC分类号： H01L27/092

摘要： The metal layers embedded into the contact holes of various kinds in shape are used as the lines and are employed as the lines for controlling the substrate bias. The first-layer metal line layers are made thin so as to be also employed as the lines for controlling the substrate bias. Moreover, the second-layer metal line layers are employed as the copper line layers. Thereby, a semiconductor integrated circuit which allows a high-speed and low-power operation is provided with a small area and without increasing the number of the masks.

公开(公告)号：US20040217432A1

公开(公告)日：2004-11-04

申请号：US10848473

申请日：2004-05-17

申请人： Hitachi, Ltd.

发明人： Tomio Iwasaki ,  Hiroshi Moriya ,  Hideo Miura ,  Shuji Ikeda

IPC分类号： H01L029/76 ,  H01L031/062

CPC分类号： H01L21/823462 ,  H01L21/28097 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28518 ,  H01L21/31604 ,  H01L21/823412 ,  H01L27/1085 ,  H01L27/10873 ,  H01L29/045 ,  H01L29/4908 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/78696

摘要： Diffusion layers 2-5 are formed on a silicon substrate 1, and gate dielectric films 6, 7 and gate electrodes 8, 9 are formed on these diffusion layers 2-5 so as to be MOS transistors. Zirconium oxide or hafnium oxide is used as a major component of gate dielectric films 6, 7. Gate dielectric films 6, 7 are formed, for example, by CVD. As substrate 1, there is used one of which the surface is (111) crystal face so as to prevent diffusion of oxygen into silicon substrate 1 or gate electrodes 8, 9. In case of using a substrate of which the surface is (111) crystal face, diffusion coefficient of oxygen is less than {fraction (1/100)} of the case in which a silicon substrate of which the surface is (001) crystal face is used, and oxygen diffusion is controlled. Thus, oxygen diffusion is controlled, generation of leakage current is prevented and properties are improved. There is realized a semiconductor device having high reliability and capable of preventing deterioration of characteristics concomitant to miniaturization.

摘要翻译： 在硅衬底1上形成扩散层2-5，并且在这些扩散层2-5上形成栅电介质膜6,7和栅电极8,9，以便成为MOS晶体管。 氧化锆或氧化铪被用作栅极电介质膜6,7的主要成分。例如通过CVD形成栅极绝缘膜6,7。 作为基板1，使用表面为（111）晶面的其中之一，以防止氧扩散到硅基板1或栅电极8,9中。在使用其表面为（111）的基板的情况下， 晶面，氧的扩散系数小于{分数（表面为（001）晶面的硅衬底的情况下的1/100，并且控制氧扩散，因此控制氧扩散， 防止了漏电流的产生，提高了性能，实现了具有高可靠性且能够防止伴随小型化的特性劣化的半导体器件。

公开(公告)号：US20030030117A1

公开(公告)日：2003-02-13

申请号：US10155833

申请日：2002-05-22

申请人： Hitachi, Ltd.

发明人： Tomio Iwasaki ,  Hiroshi Moriya ,  Hideo Miura ,  Shuji Ikeda

IPC分类号： H01L029/76 ,  H01L029/94 ,  H01L031/062

CPC分类号： H01L21/823462 ,  H01L21/28097 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28518 ,  H01L21/31604 ,  H01L21/823412 ,  H01L27/1085 ,  H01L27/10873 ,  H01L29/045 ,  H01L29/4908 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/78696

摘要： Diffusion layers 2-5 are formed on a silicon substrate 1, and gate dielectric films 6, 7 and gate electrodes 8, 9 are formed on these diffusion layers 2-5 so as to be MOS transistors. Zirconium oxide or hafnium oxide is used as a major component of gate dielectric films 6, 7. Gate dielectric films 6, 7 are formed, for example, by CVD. As substrate 1, there is used one of which the surface is (111) crystal face so as to prevent diffusion of oxygen into silicon substrate 1 or gate electrodes 8, 9. In case of using a substrate of which the surface is (111) crystal face, diffusion coefficient of oxygen is less than {fraction (1/100)} of the case in which a silicon substrate of which the surface is (001) crystal face is used, and oxygen diffusion is controlled. Thus, oxygen diffusion is controlled, generation of leakage current is prevented and properties are improved. There is realized a semiconductor device having high reliability and capable of preventing deterioration of characteristics concomitant to miniaturization.

摘要翻译： 在硅衬底1上形成扩散层2-5，并且在这些扩散层2-5上形成栅电介质膜6,7和栅电极8,9，以便成为MOS晶体管。 氧化锆或氧化铪被用作栅极电介质膜6,7的主要成分。例如通过CVD形成栅极绝缘膜6,7。 作为基板1，使用表面为（111）晶面的其中之一，以防止氧扩散到硅基板1或栅电极8,9中。在使用其表面为（111）的基板的情况下， 在使用表面为（001）晶面的硅衬底的情况下，氧的扩散系数小于氧的扩散系数的1/100，并且控制氧扩散。 因此，控制氧扩散，防止漏电流的产生，提高性能。 实现了具有高可靠性并且能够防止伴随小型化的特性劣化的半导体器件。

公开(公告)号：US20040150053A1

公开(公告)日：2004-08-05

申请号：US10761311

申请日：2004-01-22

申请人： Hitachi, Ltd.

发明人： Koichiro Ishibashi ,  Shuji Ikeda ,  Harumi Wakimoto ,  Kenichi Kuroda

IPC分类号： H01L029/76

CPC分类号： H01L27/092

摘要： The metal layers embedded into the contact holes of various kinds in shape are used as the lines and are employed as the lines for controlling the substrate bias. The first-layer metal line layers are made thin so as to be also employed as the lines for controlling the substrate bias. Moreover, the second-layer metal line layers are employed as the copper line layers. Thereby, a semiconductor integrated circuit which allows a high-speed and low-power operation is provided with a small area and without increasing the number of the masks.

摘要翻译： 嵌入到各种形状的接触孔中的金属层用作线，并且用作用于控制衬底偏压的线。 使第一层金属线层薄，从而也用作用于控制衬底偏压的线。 此外，第二层金属线层用作铜线层。 因此，允许高速和低功率操作的半导体集成电路具有小面积并且不增加掩模的数量。

公开(公告)号：US20030067046A1

公开(公告)日：2003-04-10

申请号：US10299197

申请日：2002-11-18

申请人： Hitachi, Ltd.

发明人： Tomio Iwasaki ,  Hiroshi Moriya ,  Hideo Miura ,  Shuji Ikeda

IPC分类号： H01L029/76

CPC分类号： H01L29/517 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/10873 ,  H01L28/56 ,  H01L28/57 ,  H01L29/4975 ,  H01L29/513

摘要： A semiconductor device has a gate dielectric film formed of zirconium oxide or hafnium oxide as a chief material and a gate electrode film in contact with the gate dielectric film on one principal surface side of a silicon substrate. The gate dielectric film contains an addition element to prevent diffusion of oxygen.