公开(公告)号：US07941734B2

公开(公告)日：2011-05-10

申请号：US12196321

申请日：2008-08-22

申请人： Hsie-Chia Chang ,  Jau-Yet Wu ,  Yen-Chin Liao

发明人： Hsie-Chia Chang ,  Jau-Yet Wu ,  Yen-Chin Liao

IPC分类号： H03M13/00

CPC分类号： H03M13/1545 ,  H03M13/153 ,  H03M13/6508

摘要： The present invention proposes a method and apparatus for decoding BCH codes and Reed-Solomon codes, in which a modified Berlekamp-Massey algorithm is used to perform the decoding process and the efficiency of the decoder can be improved by re-defining the error locating polynomial as a reverse error locating polynomial, while the operation of the decoding process can be further realized by a common re-configurable module. Furthermore, the architecture of the decoder is consisted of a plurality of sets of re-configurable modules in order to provide parallel operations with different degrees of parallel so that the decoding speed requirement of the decoder in different applications can be satisfied.

摘要翻译： 本发明提出了一种用于对BCH码和里德 - 所罗门码进行解码的方法和装置，其中使用修正的Berlekamp-Massey算法来执行解码过程，并且可以通过重新定义误差定位多项式来提高解码器的效率 作为反向错误定位多项式，而解码处理的操作可以通过共同的可重新配置的模块进一步实现。 此外，解码器的架构由多组可重新配置的模块组成，以提供具有不同并行度的并行操作，从而可以满足解码器在不同应用中的解码速度要求。

公开(公告)号：US20080189346A1

公开(公告)日：2008-08-07

申请号：US11780090

申请日：2007-07-19

申请人： Jau-Yet WU ,  Hsie-Chia Chang

发明人： Jau-Yet WU ,  Hsie-Chia Chang

IPC分类号： G06F7/38 ,  H04K1/00

CPC分类号： G06F7/726 ,  G06F2207/7209

摘要： A method for realizing a finite field divider architecture is proposed, in which all standard basis of a divider are transformed into the composite field basis, and the circuit is realized using subfield multiplier, squarer, adder and lookup table over this composite field. The user can finish a division operation within one clock cycle and accomplish the requirement of low complexity. In many finite field operations, divider circuits like this are very helpful to RS/BCH decoders or ECC/Security processors.

摘要翻译： 提出了一种实现有限域分频器架构的方法，其中分频器的所有标准基础被转换为复合场基，并且在该复合场上使用子场乘法器，平方器，加法器和查找表来实现电路。 用户可以在一个时钟周期内完成除法运算，达到低复杂度的要求。 在许多有限的现场操作中，像这样的分频电路对RS / BCH解码器或ECC /安全处理器非常有用。

公开(公告)号：US07631250B2

公开(公告)日：2009-12-08

申请号：US11492579

申请日：2006-07-25

申请人： Yen-Chin Liao ,  Chien-Ching Lin ,  Hsie-Chia Chang ,  Chih-Wei Liu

发明人： Yen-Chin Liao ,  Chien-Ching Lin ,  Hsie-Chia Chang ,  Chih-Wei Liu

IPC分类号： G06F11/00

CPC分类号： H03M13/1122 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/6583

摘要： A self-compensation method includes: firstly using a min-sum algorithm to derive multiple output values in order to approach a operational result of the checking side of a belief-propagation; and then checking the present iteration number of decoding based on a checking rule; and finally, if in the previous step the present iteration number is identified with a to-be-corrected state, then performing a compensation procedure on the multiple output values, wherein the compensation term is dynamically selected in accordance with an input value of the checking nodes of the belief-propagation. The invention also provides an automatic compensation apparatus, which consists of devices such as a min-sum operating unit, and a dynamic quantization control unit, etc., which can be used, while executing the invented method described above, to decode the belief-propagation algorithm.

摘要翻译： 自补偿方法包括：首先使用最小和算法导出多个输出值，以接近置信传播的检验侧的运算结果; 然后根据检查规则检查当前迭代次数; 最后，如果在前一步骤中以当前迭代次数被识别为待校正状态，则对多个输出值执行补偿过程，其中根据检查的输入值来动态地选择补偿项 信念传播的节点。 本发明还提供了一种自动补偿装置，其包括诸如最小和运算单元和动态量化控制单元等的装置，其可以在执行上述发明的方法时使用，以解码信念 - 传播算法。

公开(公告)号：US20110185000A1

公开(公告)日：2011-07-28

申请号：US12932530

申请日：2011-02-28

申请人： Yen-Chin Liao ,  Hsie-Chia Chang

发明人： Yen-Chin Liao ,  Hsie-Chia Chang

IPC分类号： G06F7/52

CPC分类号： G06F7/523 ,  G06F7/49942 ,  H04L27/2655

摘要： A low-error reduced-width multiplier is provided by the present invention. The multiplier can dynamically compensate the truncation error. The compensation value is derived by the dependencies among the multiplier partial products, and thus, can be analyzed according to the multiplication type and the multiplier input statistics.

摘要翻译： 本发明提供了低误差减小倍数。 乘数可以动态补偿截断误差。 补偿值由乘数部分乘积之间的相关性导出，因此可以根据乘法类型和乘数输入统计量进行分析。

公开(公告)号：US20090037799A1

公开(公告)日：2009-02-05

申请号：US11939119

申请日：2007-11-13

申请人： Chih-Hao LIU ,  Yen-Chin Liao ,  Chen-Yi Lee ,  Hsie-Chia Chang ,  Yarsun Hsu

发明人： Chih-Hao LIU ,  Yen-Chin Liao ,  Chen-Yi Lee ,  Hsie-Chia Chang ,  Yarsun Hsu

IPC分类号： H03M13/47 ,  G06F11/00

CPC分类号： H03M13/1137 ,  H03M13/1114 ,  H03M13/658 ,  H03M13/6591

摘要： An operating method applied to low density parity check (LDPC) decoders and the circuit thereof are proposed, in which original bit nodes are incorporated into check nodes for simultaneous operation. The bit node messages are generated according to the different between the newly generated check messages and the previously check node messages. The bit node messages can be updated immediately, and the decoder throughput can be improved. In the other way, the required memory of LDPC decoders can be effectively reduced, and the decoding speed can also be enhanced.

摘要翻译： 提出了一种应用于低密度奇偶校验（LDPC）解码器及其电路的操作方法，其中将原始比特节点并入校验节点以用于同时操作。 根据新生成的检查消息和先前检查节点消息之间的不同，生成位节点消息。 可以立即更新位节点消息，并且可以提高解码器吞吐量。 另一方面，可以有效地减少LDPC解码器所需的存储器，并且也可以提高解码速度。

公开(公告)号：US20070283213A1

公开(公告)日：2007-12-06

申请号：US11492579

申请日：2006-07-25

申请人： Yen-Chin Liao ,  Chien-Ching Lin ,  Hsie-Chia Chang ,  Chih-Wei Liu

发明人： Yen-Chin Liao ,  Chien-Ching Lin ,  Hsie-Chia Chang ,  Chih-Wei Liu

IPC分类号： H03M13/00

CPC分类号： H03M13/1122 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/6583

摘要： A self-compensation method includes: firstly using a min-sum algorithm to derive multiple output values in order to approach a operational result of the checking side of a belief-propagation; and then checking the present iteration number of decoding based on a checking rule; and finally, if in the previous step the present iteration number is identified with a to-be-corrected state, then performing a compensation procedure on the multiple output values, wherein the compensation term is dynamically selected in accordance with an input value of the checking nodes of the belief-propagation. The invention also provides an automatic compensation apparatus, which consists of devices such as a min-sum operating unit, and a dynamic quantization control unit, etc., which can be used, while executing the invented method described above, to decode the belief-propagation algorithm.

摘要翻译： 自补偿方法包括：首先使用最小和算法导出多个输出值，以接近置信传播的检验侧的运算结果; 然后根据检查规则检查当前迭代次数; 最后，如果在前一步骤中以当前迭代次数被识别为待校正状态，则对多个输出值执行补偿过程，其中根据检查的输入值来动态地选择补偿项 信念传播的节点。 本发明还提供了一种自动补偿装置，其包括诸如最小和运算单元和动态量化控制单元等的装置，其可以在执行上述发明的方法时使用，以解码信念 - 传播算法。

公开(公告)号：US08255775B2

公开(公告)日：2012-08-28

申请号：US12182214

申请日：2008-07-30

申请人： Hsie-Chia Chang ,  Yen-Chin Liao

发明人： Hsie-Chia Chang ,  Yen-Chin Liao

IPC分类号： G06F11/00

CPC分类号： H04L25/03242 ,  H04L1/0045 ,  H04L1/06 ,  H04L25/067 ,  H04L2025/03426

摘要： The present invention discloses a candidate list augmentation apparatus with dynamic compensation in the coded MIMO systems. The proposed path augmentation technique in the present invention can expand the candidate paths derived from the detector to a distinct and larger list before computing the soft value of each bit. Consequently, the detector is allowed to deliver a smaller list, leading to reduction in computation complexity. Moreover, an additive correction term is introduced to dynamically compensate the approximation inaccuracy in the soft value generation, which improves the efficiency and performance of the coded MIMO systems.

摘要翻译： 本发明公开了一种在编码的MIMO系统中具有动态补偿的候选列表增强装置。 本发明中提出的路径增加技术可以在计算每个比特的软值之前将从检测器导出的候选路径扩展到不同的和较大的列表。 因此，允许检测器递送较小的列表，导致计算复杂性的降低。 此外，引入加法校正项以动态地补偿软值生成中的近似不准确性，这提高了编码的MIMO系统的效率和性能。

公开(公告)号：US08108762B2

公开(公告)日：2012-01-31

申请号：US11939119

申请日：2007-11-13

申请人： Chih-Hao Liu ,  Yen-Chin Liao ,  Chen-Yi Lee ,  Hsie-Chia Chang ,  Yarsun Hsu

发明人： Chih-Hao Liu ,  Yen-Chin Liao ,  Chen-Yi Lee ,  Hsie-Chia Chang ,  Yarsun Hsu

IPC分类号： G06F11/00 ,  H03M13/00

CPC分类号： H03M13/1137 ,  H03M13/1114 ,  H03M13/658 ,  H03M13/6591

摘要： An operating method and a circuit for low density parity check (LDPC) decoders, in which original bit nodes are incorporated into check nodes for simultaneous operation. The bit node messages are generated according to the difference between the newly generated check messages and the previous check node messages. The bit node messages can be updated immediately, and the decoder throughput can be improved. The required memory of LDPC decoders can be effectively reduced, and the decoding speed can also be enhanced.

摘要翻译： 一种用于低密度奇偶校验（LDPC）解码器的操作方法和电路，其中将原始比特节点并入校验节点用于同时操作。 根据新生成的检查消息和先前检查节点消息之间的差异来生成位节点消息。 可以立即更新位节点消息，并且可以提高解码器吞吐量。 可以有效地减少LDPC解码器所需的存储器，并且还可以提高解码速度。

公开(公告)号：US20080159441A1

公开(公告)日：2008-07-03

申请号：US11787716

申请日：2007-04-17

申请人： Yen-Chin Liao ,  Hsie-Chia Chang

发明人： Yen-Chin Liao ,  Hsie-Chia Chang

IPC分类号： H04L27/00

CPC分类号： G06F7/523 ,  G06F7/4991 ,  H04L27/265

摘要： A low-error reduced-width multiplier is provided by the present invention. The multiplier can dynamically compensate the truncation error. The compensation value is derived by the dependencies among the multiplier partial products, and thus, can be analyzed according to the multiplication type and the multiplier input statistics.

摘要翻译： 本发明提供了低误差减小倍数。 乘数可以动态补偿截断误差。 补偿值由乘数部分乘积之间的相关性导出，因此可以根据乘法类型和乘数输入统计量进行分析。

公开(公告)号：US08639738B2

公开(公告)日：2014-01-28

申请号：US12932530

申请日：2011-02-28

申请人： Yen-Chin Liao ,  Hsie-Chia Chang

发明人： Yen-Chin Liao ,  Hsie-Chia Chang

IPC分类号： G06F7/38 ,  G06F7/52

CPC分类号： G06F7/523 ,  G06F7/49942 ,  H04L27/2655

摘要： A low-error reduced-width multiplier is provided by the present invention. The multiplier can dynamically compensate the truncation error. The compensation value is derived by the dependencies among the multiplier partial products, and thus, can be analyzed according to the multiplication type and the multiplier input statistics.

摘要翻译： 本发明提供了低误差减小倍数。 乘数可以动态补偿截断误差。 补偿值由乘数部分乘积之间的相关性导出，因此可以根据乘法类型和乘数输入统计量进行分析。