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    Measurement transmission method enabling network loading to be reduced
    1.
    发明授权
    Measurement transmission method enabling network loading to be reduced 有权

    公开(公告)号：US11991264B2

    公开(公告)日：2024-05-21

    申请号：US17378168

    申请日：2021-07-16

    Applicant: SAGEMCOM ENERGY & TELECOM SAS

    Inventor： Henri Teboulle

    IPC: H04L29/06 ,  G06F7/499 ,  H04L67/12 ,  H04L69/22

    CPC classification number: H04L69/22 ,  G06F7/49942 ,  H04L67/12

    Abstract: A transmission method for transmitting measurements is taken by a fluid meter during successive measurement periods, each subdivided into successive time intervals. The measurements comprise first measurements, each representative of a quantity of fluid distributed during a respective one of the time intervals. The transmission method includes, for each measurement period, the step of producing and then transmitting at least one measurement frame such that: when the number of first measurements that are equal to zero is strictly less than a predetermined number during said measurement period, then the measurement frame is a normal measurement frame; otherwise the measurement frame is a compact measurement frame that, when there is at least one first measurement that is not equal to zero, comprises both preliminary data comprising identification data for identifying active time intervals and also compact first measurement data comprising only said non-zero first measurements ordered in a predefined order.

    Controlled-precision iterative arithmetic logic unit
    6.
    发明授权
    Controlled-precision iterative arithmetic logic unit 有权
    控制精度迭代算术逻辑单元

    公开(公告)号：US09146706B2

    公开(公告)日：2015-09-29

    申请号：US11381870

    申请日：2006-05-05

    Applicant: Kenneth Alan Dockser

    Inventor： Kenneth Alan Dockser

    IPC: G06F7/499 ,  G06F7/537 ,  G06F7/483

    CPC classification number: G06F7/49942 ,  G06F7/483 ,  G06F7/49947 ,  G06F7/537 ,  G06F2207/382

    Abstract: A controlled-precision Iterative Arithmetic Logic Unit (IALU) included in a processor produces sub-precision results, i.e. results having a bit precision less than full precision. In one embodiment, the controlled-precision IALU comprises an arithmetic logic circuit and a precision control circuit. The arithmetic logic circuit is configured to iteratively process operands of a first bit precision to obtain a result. The precision control circuit is configured to end the iterative operand processing when the result achieves a programmed second bit precision less than the first bit precision. In one embodiment, the precision control circuit causes the arithmetic logic circuit to end the iterative operand processing in response to an indicator received by the control circuit. The controlled-precision IALU further comprises rounding logic configured to round the sub-precision result.

    Abstract translation: 包含在处理器中的受控精密迭代算术逻辑单元（IALU）产生子精度结果，即具有小于全精度的位精度的结果。 在一个实施例中，受控精度IALU包括算术逻辑电路和精密控制电路。 算术逻辑电路被配置为迭代地处理第一位精度的操作数以获得结果。 精度控制电路被配置为当结果达到低于第一位精度的编程的第二位精度时结束迭代操作数处理。 在一个实施例中，精密控制电路使得算术逻辑电路响应于由控制电路接收的指示器来结束迭代操作数处理。 受控精度IALU还包括被配置为舍入子精度结果的舍入逻辑。

    System and method for testing whether a result is correctly rounded
    7.
    发明授权
    System and method for testing whether a result is correctly rounded 有权
    用于测试结果是否正确四舍五入的系统和方法

    公开(公告)号：US08775494B2

    公开(公告)日：2014-07-08

    申请号：US13038193

    申请日：2011-03-01

    Applicant: Alexandru Fit-Florea

    Inventor： Alexandru Fit-Florea

    IPC: G06F7/38

    CPC classification number: G06F7/483 ,  G06F7/4873 ,  G06F7/49942 ,  G06F7/5525 ,  G06F2207/5355 ,  G06F2207/5356

    Abstract: A computer-implemented method for executing a floating-point calculation where an exact value of an associated result cannot be expressed as a floating-point value is disclosed. The method involves: generating an estimate of the associated result and storing the estimate in memory; calculating an amount of error for the estimate; determining whether the amount of error is less than or equal to a threshold of error for the associated result; and if the amount of error is less than or equal to the threshold of error, then concluding that the estimate of the associated result is a correctly rounded result of the floating-point calculation; or if the amount of error is greater than the threshold of error, then testing whether the floating-point calculation constitutes an exception case.

    Abstract translation: 公开了一种用于执行浮点计算的计算机实现的方法，其中相关联的结果的精确值不能被表示为浮点值。 该方法包括：产生关联结果的估计并将估计存储在存储器中; 计算估计的误差量; 确定误差量是否小于或等于相关结果的误差阈值; 并且如果误差量小于或等于误差阈值，则认为相关结果的估计是浮点计算的正确舍入结果; 或者如果错误量大于错误阈值，则测试浮点计算是否构成异常情况。

    Sine/cosine generator
    8.
    发明授权
    Sine/cosine generator 有权
    正弦/余弦发生器

    公开(公告)号：US08200728B2

    公开(公告)日：2012-06-12

    申请号：US12129654

    申请日：2008-05-29

    Applicant: Alan J. Michaels ,  David B. Chester

    Inventor： Alan J. Michaels ,  David B. Chester

    IPC: G06F1/02

    CPC classification number: G06F7/548 ,  G06F1/03 ,  G06F7/49942

    Abstract: A method (300) for generating a sine and cosine of an input angle (Ø102). The method involves decomposing Ø102 to an octant or quadrant, a coarse angle (A), and a fine angle (B), determining cos(A), and determining sin(A). The method also involves decomposing cos(A) and sin(A) to a most significant word (MSW) and a least significant word (LSW). The method further involves computing an approximation of 1−cos(B), an approximation of sin(B), and a plurality of products (P1, . . . , P4) using the MSWs and approximations. The method involves computing approximations of cos(Ø′102) and sin(Ø′102) using the values for cos(A), sin(A), and P1, . . . , P4. The method involves scaling the approximations of cos(Ø′102) and sin(Ø′102) to a desired resolution.

    Abstract translation: 一种用于产生输入角度的正弦和余弦的方法（300）（Ø102）。 该方法包括将Ø102分解为八分圆或象限，粗角（A）和细角（B），确定cos（A），并确定sin（A）。 该方法还涉及将cos（A）和sin（A）分解为最高有效字（MSW）和最低有效字（LSW）。 该方法还包括使用MSW和近似来计算1-cos（B）的近似，sin（B）的近似以及多个乘积（P1，...，P4）。 该方法包括使用cos（A），sin（A）和P1的值来计算cos（Ø'102）和sin（Ø'102）的近似值。 。 。 ，P4。 该方法包括将cos（Ø'102）和sin（Ø'102）的近似值缩放到所需的分辨率。

    Method and a circuit using an associative calculator for calculating a sequence of non-associative operations
    9.
    发明授权
    Method and a circuit using an associative calculator for calculating a sequence of non-associative operations 有权
    方法和使用关联计算器计算非关联操作序列的电路

    公开(公告)号：US07991817B2

    公开(公告)日：2011-08-02

    申请号：US11655745

    申请日：2007-01-19

    Applicant: Andre M. DeHon ,  Nachiket Kapre

    Inventor： Andre M. DeHon ,  Nachiket Kapre

    IPC: G06F7/42 ,  G06F7/38

    CPC classification number: G06F7/49942 ,  G06F7/485 ,  G06F7/508 ,  G06F7/509

    Abstract: An apparatus and method that use an associative calculator for calculating a sequence of non-associative operations on a set of input data, comprising: using the associative calculator to calculate from the set of input data an evaluated value of each operation of said sequence as if the non-associative operations were associative operations; detecting if some of the evaluated values are erroneous; if there are erroneous evaluated values, correcting the erroneous evaluated values; and if there are no erroneous evaluated value, outputting as the result of the sequence of non-associative operations the evaluated value of the last operation of the sequence.

    Abstract translation: 一种使用关联计算器来计算一组输入数据的非关联操作序列的装置和方法，包括：使用所述关联计算器从所述输入数据集合中计算所述序列的每个操作的估计值，如同 非关联操作是关联操作; 检测某些评估值是否错误; 如果存在错误的评估值，则校正错误的评估值; 并且如果没有错误的评估值，则作为非关联操作序列的结果输出序列的最后操作的评估值。

    System and method for implementing irregular data formats
    10.
    发明授权
    System and method for implementing irregular data formats 失效
    用于实现不规则数据格式的系统和方法

    公开(公告)号：US07885992B2

    公开(公告)日：2011-02-08

    申请号：US11759512

    申请日：2007-06-07

    Applicant: Manuel F. Richey ,  Timothy P. Gibson

    Inventor： Manuel F. Richey ,  Timothy P. Gibson

    IPC: G06F7/483

    CPC classification number: G06F7/49942 ,  G06F7/483

    Abstract: A computer system comprises a processing unit configured to process fixed size data words comprising at least one exponent field of variable size and a mantissa of variable size; an input device configured to provide data words to the processing unit; and an output device configured to output data words processed by the processing unit.

    Abstract translation: 计算机系统包括处理单元，其被配置为处理包括可变大小的至少一个指数字段和可变大小的尾数的固定大小的数据字; 被配置为向所述处理单元提供数据字的输入装置; 以及输出装置，被配置为输出由所述处理单元处理的数据字。

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