公开(公告)号：US20090037799A1

公开(公告)日：2009-02-05

申请号：US11939119

申请日：2007-11-13

申请人： Chih-Hao LIU ,  Yen-Chin Liao ,  Chen-Yi Lee ,  Hsie-Chia Chang ,  Yarsun Hsu

发明人： Chih-Hao LIU ,  Yen-Chin Liao ,  Chen-Yi Lee ,  Hsie-Chia Chang ,  Yarsun Hsu

IPC分类号： H03M13/47 ,  G06F11/00

CPC分类号： H03M13/1137 ,  H03M13/1114 ,  H03M13/658 ,  H03M13/6591

摘要： An operating method applied to low density parity check (LDPC) decoders and the circuit thereof are proposed, in which original bit nodes are incorporated into check nodes for simultaneous operation. The bit node messages are generated according to the different between the newly generated check messages and the previously check node messages. The bit node messages can be updated immediately, and the decoder throughput can be improved. In the other way, the required memory of LDPC decoders can be effectively reduced, and the decoding speed can also be enhanced.

摘要翻译： 提出了一种应用于低密度奇偶校验（LDPC）解码器及其电路的操作方法，其中将原始比特节点并入校验节点以用于同时操作。 根据新生成的检查消息和先前检查节点消息之间的不同，生成位节点消息。 可以立即更新位节点消息，并且可以提高解码器吞吐量。 另一方面，可以有效地减少LDPC解码器所需的存储器，并且也可以提高解码速度。

公开(公告)号：US08108762B2

公开(公告)日：2012-01-31

申请号：US11939119

申请日：2007-11-13

申请人： Chih-Hao Liu ,  Yen-Chin Liao ,  Chen-Yi Lee ,  Hsie-Chia Chang ,  Yarsun Hsu

发明人： Chih-Hao Liu ,  Yen-Chin Liao ,  Chen-Yi Lee ,  Hsie-Chia Chang ,  Yarsun Hsu

IPC分类号： G06F11/00 ,  H03M13/00

CPC分类号： H03M13/1137 ,  H03M13/1114 ,  H03M13/658 ,  H03M13/6591

摘要： An operating method and a circuit for low density parity check (LDPC) decoders, in which original bit nodes are incorporated into check nodes for simultaneous operation. The bit node messages are generated according to the difference between the newly generated check messages and the previous check node messages. The bit node messages can be updated immediately, and the decoder throughput can be improved. The required memory of LDPC decoders can be effectively reduced, and the decoding speed can also be enhanced.

摘要翻译： 一种用于低密度奇偶校验（LDPC）解码器的操作方法和电路，其中将原始比特节点并入校验节点用于同时操作。 根据新生成的检查消息和先前检查节点消息之间的差异来生成位节点消息。 可以立即更新位节点消息，并且可以提高解码器吞吐量。 可以有效地减少LDPC解码器所需的存储器，并且还可以提高解码速度。

公开(公告)号：US20090146849A1

公开(公告)日：2009-06-11

申请号：US12048101

申请日：2008-03-13

申请人： Chih-Hao LIU ,  Chien-Ching Lin ,  Chen-Yi Lee ,  Hsie-Chia Chang ,  Yarsun Hsu

发明人： Chih-Hao LIU ,  Chien-Ching Lin ,  Chen-Yi Lee ,  Hsie-Chia Chang ,  Yarsun Hsu

IPC分类号： H03M7/00

CPC分类号： H03M13/116 ,  H03M13/1105 ,  H03M13/1111 ,  H03M13/6561

摘要： A multi-mode multi-parallelism data exchange method and the device thereof are proposed to apply to a check node operator or a bit node operator. The proposed method comprises the steps of: duplicating part or all of an original shift data as a duplicated shift data; combining the original shift data and the duplicated shift data to form a data block; and using a data block as the unit to shift this data block so as to conveniently retrieve shift data from the shifted data block. With a maximum z factor circuit and duplication of part of data, specifications of different shift sizes can be supported. The functions of shifters of several sizes can therefore be accomplished with the minimum complexity.

摘要翻译： 提出了一种多模式多并行数据交换方法及其装置，以应用于校验节点运算符或位节点运算符。 所提出的方法包括以下步骤：将原始移位数据的一部分或全部复制为复制移位数据; 组合原始移位数据和复制的移位数据以形成数据块; 并且使用数据块作为单元来移位该数据块，从而便于从移位的数据块检索移位数据。 通过最大的z因子电路和部分数据的重复，可以支持不同位移大小的规范。 因此可以以最小的复杂度来实现几种尺寸的移位器的功能。

公开(公告)号：US07719442B2

公开(公告)日：2010-05-18

申请号：US12048101

申请日：2008-03-13

申请人： Chih-Hao Liu ,  Chien-Ching Lin ,  Chen-Yi Lee ,  Hsie-Chia Chang ,  Yarsun Hsu

发明人： Chih-Hao Liu ,  Chien-Ching Lin ,  Chen-Yi Lee ,  Hsie-Chia Chang ,  Yarsun Hsu

IPC分类号： H03M7/34

CPC分类号： H03M13/116 ,  H03M13/1105 ,  H03M13/1111 ,  H03M13/6561

摘要： A multi-mode multi-parallelism data exchange method and the device thereof are proposed to apply to a check node operator or a bit node operator. The proposed method comprises the steps of: duplicating part or all of an original shift data as a duplicated shift data; combining the original shift data and the duplicated shift data to form a data block; and using a data block as the unit to shift this data block so as to conveniently retrieve shift data from the shifted data block. With a maximum z factor circuit and duplication of part of data, specifications of different shift sizes can be supported. The functions of shifters of several sizes can therefore be accomplished with the minimum complexity.

摘要翻译： 提出了一种多模式多并行数据交换方法及其装置，以应用于校验节点运算符或位节点运算符。 所提出的方法包括以下步骤：将原始移位数据的一部分或全部复制为复制移位数据; 组合原始移位数据和复制的移位数据以形成数据块; 并且使用数据块作为单元来移位该数据块，从而便于从移位的数据块检索移位数据。 通过最大的z因子电路和部分数据的重复，可以支持不同位移大小的规范。 因此可以以最小的复杂度来实现几种尺寸的移位器的功能。

公开(公告)号：US07724772B2

公开(公告)日：2010-05-25

申请号：US11802028

申请日：2007-05-18

申请人： Chen-Yi Lee ,  Chih-Hao Liu ,  Chien-Ching Lin ,  Hsie-Chia Chang ,  Yar-Sun Hsu

发明人： Chen-Yi Lee ,  Chih-Hao Liu ,  Chien-Ching Lin ,  Hsie-Chia Chang ,  Yar-Sun Hsu

IPC分类号： H04J3/16

CPC分类号： H04L1/0052 ,  H03M13/116 ,  H03M13/6502 ,  H03M13/6519 ,  H03M13/6527 ,  H03M13/6544 ,  H04L2001/0097

摘要： A method and apparatus for switching data in communication system which comprises of mainly a conversion circuit to receive source data possessing real coding dimension and covert it to converted data possessing tolerable coding dimension; judgment bit is set in the converted data to designate the data as source data or not. Later on, shift circuit is used to shift the converted data in certain amount so as to generate a shifted data; meanwhile, the lowest bit and highest bit of shifted data are used to start acquiring real coding dimension to be used respectively as a first data and a second data, or by changing the pattern of acquiring the first data, then the highest bit minus the real coding dimension bit as the starting bit of the first data, and acquiring the real coding dimension from the side of the lowest bit. Finally, a comparison and selection circuit is used to compare the corresponding judgment bit in the first and the second data and to output an output data, wherein output data is source data with the above-mentioned amount of shift.

摘要翻译： 一种用于在通信系统中切换数据的方法和装置，其主要包括：转换电路，用于接收具有实际编码维度的源数据，并将其转换为具有可容忍编码维度的转换数据; 在转换的数据中设置判断位以将数据指定为源数据。 稍后，使用移位电路将转换后的数据移动到一定量，以产生移位数据; 同时，移位数据的最低位和最高位被用于开始获取要被分别用作第一数据和第二数据的实数编码维度，或通过改变获取第一数据的模式，然后最高位减去实数 编码维度位作为第一数据的起始位，并且从最低位的侧面获取实际编码维度。 最后，比较和选择电路用于比较第一和第二数据中相应的判断位，并输出输出数据，其中输出数据是具有上述移位量的源数据。

公开(公告)号：US20080198843A1

公开(公告)日：2008-08-21

申请号：US11802028

申请日：2007-05-18

申请人： Chen-Yi Lee ,  Chih-Hao Liu ,  Chien-Ching Lin ,  Hsie-Chia Chang ,  Yar-Sun Hsu

发明人： Chen-Yi Lee ,  Chih-Hao Liu ,  Chien-Ching Lin ,  Hsie-Chia Chang ,  Yar-Sun Hsu

IPC分类号： H04L12/50

CPC分类号： H04L1/0052 ,  H03M13/116 ,  H03M13/6502 ,  H03M13/6519 ,  H03M13/6527 ,  H03M13/6544 ,  H04L2001/0097

摘要： A method and apparatus for switching data in communication system which comprises of mainly a conversion circuit to receive source data possessing real coding dimension and covert it to converted data possessing tolerable coding dimension; judgment bit is set in the converted data to designate the data as source data or not. Later on, shift circuit is used to shift the converted data in certain amount so as to generate a shifted data; meanwhile, the lowest bit and highest bit of shifted data are used to start acquiring real coding dimension to be used respectively as a first data and a second data, or by changing the pattern of acquiring the first data, then the highest bit minus the real coding dimension bit as the starting bit of the first data, and acquiring the real coding dimension from the side of the lowest bit. Finally, a comparison and selection circuit is used to compare the corresponding judgment bit in the first and the second data and to output an output data, wherein output data is source data with the above-mentioned amount of shift.

摘要翻译： 一种用于在通信系统中切换数据的方法和装置，其主要包括：转换电路，用于接收具有实际编码维度的源数据，并将其转换为具有可容忍编码维度的转换数据; 在转换的数据中设置判断位以将数据指定为源数据。 稍后，使用移位电路将转换后的数据移动到一定量，以产生移位数据; 同时，移位数据的最低位和最高位被用于开始获取要被分别用作第一数据和第二数据的实数编码维度，或通过改变获取第一数据的模式，然后最高位减去实数 编码维度位作为第一数据的起始位，并且从最低位的侧面获取实际编码维度。 最后，比较和选择电路用于比较第一和第二数据中相应的判断位，并输出输出数据，其中输出数据是具有上述移位量的源数据。

公开(公告)号：US07631250B2

公开(公告)日：2009-12-08

申请号：US11492579

申请日：2006-07-25

申请人： Yen-Chin Liao ,  Chien-Ching Lin ,  Hsie-Chia Chang ,  Chih-Wei Liu

发明人： Yen-Chin Liao ,  Chien-Ching Lin ,  Hsie-Chia Chang ,  Chih-Wei Liu

IPC分类号： G06F11/00

CPC分类号： H03M13/1122 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/6583

摘要： A self-compensation method includes: firstly using a min-sum algorithm to derive multiple output values in order to approach a operational result of the checking side of a belief-propagation; and then checking the present iteration number of decoding based on a checking rule; and finally, if in the previous step the present iteration number is identified with a to-be-corrected state, then performing a compensation procedure on the multiple output values, wherein the compensation term is dynamically selected in accordance with an input value of the checking nodes of the belief-propagation. The invention also provides an automatic compensation apparatus, which consists of devices such as a min-sum operating unit, and a dynamic quantization control unit, etc., which can be used, while executing the invented method described above, to decode the belief-propagation algorithm.

摘要翻译： 自补偿方法包括：首先使用最小和算法导出多个输出值，以接近置信传播的检验侧的运算结果; 然后根据检查规则检查当前迭代次数; 最后，如果在前一步骤中以当前迭代次数被识别为待校正状态，则对多个输出值执行补偿过程，其中根据检查的输入值来动态地选择补偿项 信念传播的节点。 本发明还提供了一种自动补偿装置，其包括诸如最小和运算单元和动态量化控制单元等的装置，其可以在执行上述发明的方法时使用，以解码信念 - 传播算法。

公开(公告)号：US20110185000A1

公开(公告)日：2011-07-28

申请号：US12932530

申请日：2011-02-28

申请人： Yen-Chin Liao ,  Hsie-Chia Chang

发明人： Yen-Chin Liao ,  Hsie-Chia Chang

IPC分类号： G06F7/52

CPC分类号： G06F7/523 ,  G06F7/49942 ,  H04L27/2655

摘要： A low-error reduced-width multiplier is provided by the present invention. The multiplier can dynamically compensate the truncation error. The compensation value is derived by the dependencies among the multiplier partial products, and thus, can be analyzed according to the multiplication type and the multiplier input statistics.

摘要翻译： 本发明提供了低误差减小倍数。 乘数可以动态补偿截断误差。 补偿值由乘数部分乘积之间的相关性导出，因此可以根据乘法类型和乘数输入统计量进行分析。

公开(公告)号：US20070283213A1

公开(公告)日：2007-12-06

申请号：US11492579

申请日：2006-07-25

申请人： Yen-Chin Liao ,  Chien-Ching Lin ,  Hsie-Chia Chang ,  Chih-Wei Liu

发明人： Yen-Chin Liao ,  Chien-Ching Lin ,  Hsie-Chia Chang ,  Chih-Wei Liu

IPC分类号： H03M13/00

CPC分类号： H03M13/1122 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/6583

摘要： A self-compensation method includes: firstly using a min-sum algorithm to derive multiple output values in order to approach a operational result of the checking side of a belief-propagation; and then checking the present iteration number of decoding based on a checking rule; and finally, if in the previous step the present iteration number is identified with a to-be-corrected state, then performing a compensation procedure on the multiple output values, wherein the compensation term is dynamically selected in accordance with an input value of the checking nodes of the belief-propagation. The invention also provides an automatic compensation apparatus, which consists of devices such as a min-sum operating unit, and a dynamic quantization control unit, etc., which can be used, while executing the invented method described above, to decode the belief-propagation algorithm.

摘要翻译： 自补偿方法包括：首先使用最小和算法导出多个输出值，以接近置信传播的检验侧的运算结果; 然后根据检查规则检查当前迭代次数; 最后，如果在前一步骤中以当前迭代次数被识别为待校正状态，则对多个输出值执行补偿过程，其中根据检查的输入值来动态地选择补偿项 信念传播的节点。 本发明还提供了一种自动补偿装置，其包括诸如最小和运算单元和动态量化控制单元等的装置，其可以在执行上述发明的方法时使用，以解码信念 - 传播算法。

公开(公告)号：US07941734B2

公开(公告)日：2011-05-10

申请号：US12196321

申请日：2008-08-22

申请人： Hsie-Chia Chang ,  Jau-Yet Wu ,  Yen-Chin Liao

发明人： Hsie-Chia Chang ,  Jau-Yet Wu ,  Yen-Chin Liao

IPC分类号： H03M13/00

CPC分类号： H03M13/1545 ,  H03M13/153 ,  H03M13/6508

摘要： The present invention proposes a method and apparatus for decoding BCH codes and Reed-Solomon codes, in which a modified Berlekamp-Massey algorithm is used to perform the decoding process and the efficiency of the decoder can be improved by re-defining the error locating polynomial as a reverse error locating polynomial, while the operation of the decoding process can be further realized by a common re-configurable module. Furthermore, the architecture of the decoder is consisted of a plurality of sets of re-configurable modules in order to provide parallel operations with different degrees of parallel so that the decoding speed requirement of the decoder in different applications can be satisfied.

摘要翻译： 本发明提出了一种用于对BCH码和里德 - 所罗门码进行解码的方法和装置，其中使用修正的Berlekamp-Massey算法来执行解码过程，并且可以通过重新定义误差定位多项式来提高解码器的效率 作为反向错误定位多项式，而解码处理的操作可以通过共同的可重新配置的模块进一步实现。 此外，解码器的架构由多组可重新配置的模块组成，以提供具有不同并行度的并行操作，从而可以满足解码器在不同应用中的解码速度要求。