公开(公告)号：US07631250B2

公开(公告)日：2009-12-08

申请号：US11492579

申请日：2006-07-25

申请人： Yen-Chin Liao ,  Chien-Ching Lin ,  Hsie-Chia Chang ,  Chih-Wei Liu

发明人： Yen-Chin Liao ,  Chien-Ching Lin ,  Hsie-Chia Chang ,  Chih-Wei Liu

IPC分类号： G06F11/00

CPC分类号： H03M13/1122 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/6583

摘要： A self-compensation method includes: firstly using a min-sum algorithm to derive multiple output values in order to approach a operational result of the checking side of a belief-propagation; and then checking the present iteration number of decoding based on a checking rule; and finally, if in the previous step the present iteration number is identified with a to-be-corrected state, then performing a compensation procedure on the multiple output values, wherein the compensation term is dynamically selected in accordance with an input value of the checking nodes of the belief-propagation. The invention also provides an automatic compensation apparatus, which consists of devices such as a min-sum operating unit, and a dynamic quantization control unit, etc., which can be used, while executing the invented method described above, to decode the belief-propagation algorithm.

摘要翻译： 自补偿方法包括：首先使用最小和算法导出多个输出值，以接近置信传播的检验侧的运算结果; 然后根据检查规则检查当前迭代次数; 最后，如果在前一步骤中以当前迭代次数被识别为待校正状态，则对多个输出值执行补偿过程，其中根据检查的输入值来动态地选择补偿项 信念传播的节点。 本发明还提供了一种自动补偿装置，其包括诸如最小和运算单元和动态量化控制单元等的装置，其可以在执行上述发明的方法时使用，以解码信念 - 传播算法。

公开(公告)号：US20070283213A1

公开(公告)日：2007-12-06

申请号：US11492579

申请日：2006-07-25

申请人： Yen-Chin Liao ,  Chien-Ching Lin ,  Hsie-Chia Chang ,  Chih-Wei Liu

发明人： Yen-Chin Liao ,  Chien-Ching Lin ,  Hsie-Chia Chang ,  Chih-Wei Liu

IPC分类号： H03M13/00

CPC分类号： H03M13/1122 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/6583

摘要： A self-compensation method includes: firstly using a min-sum algorithm to derive multiple output values in order to approach a operational result of the checking side of a belief-propagation; and then checking the present iteration number of decoding based on a checking rule; and finally, if in the previous step the present iteration number is identified with a to-be-corrected state, then performing a compensation procedure on the multiple output values, wherein the compensation term is dynamically selected in accordance with an input value of the checking nodes of the belief-propagation. The invention also provides an automatic compensation apparatus, which consists of devices such as a min-sum operating unit, and a dynamic quantization control unit, etc., which can be used, while executing the invented method described above, to decode the belief-propagation algorithm.

摘要翻译： 自补偿方法包括：首先使用最小和算法导出多个输出值，以接近置信传播的检验侧的运算结果; 然后根据检查规则检查当前迭代次数; 最后，如果在前一步骤中以当前迭代次数被识别为待校正状态，则对多个输出值执行补偿过程，其中根据检查的输入值来动态地选择补偿项 信念传播的节点。 本发明还提供了一种自动补偿装置，其包括诸如最小和运算单元和动态量化控制单元等的装置，其可以在执行上述发明的方法时使用，以解码信念 - 传播算法。

公开(公告)号：US20090172683A1

公开(公告)日：2009-07-02

申请号：US12107082

申请日：2008-04-22

申请人： Tai-Ji Lin ,  Tien-Wei Hsieh ,  Yuan-Hua Chu ,  Shih-Hao Ou ,  Xiang-Sheng Deng ,  Chih-Wei Liu

发明人： Tai-Ji Lin ,  Tien-Wei Hsieh ,  Yuan-Hua Chu ,  Shih-Hao Ou ,  Xiang-Sheng Deng ,  Chih-Wei Liu

IPC分类号： G06F9/46

CPC分类号： G06F9/505 ,  G06F9/3877 ,  G06F2209/5017

摘要： A multicore interface with dynamic task management capability and a task loading and offloading method thereof are provided. The method disposes a communication interface between a micro processor unit (MPU) and a digital signal processor (DSP) and dynamically manages tasks assigned by the MPU to the DSP. First, an idle processing unit of the DSP is searched, and then one of a plurality of threads of the task is assigned to the processing unit. Finally, the processing unit is activated to execute the thread. Accordingly, the communication efficiency of the multicore processor can be effectively increased while the hardware cost can be saved.

摘要翻译： 提供了具有动态任务管理功能的多核接口及其任务加载和卸载方法。 该方法在微处理器单元（MPU）和数字信号处理器（DSP）之间配置通信接口，动态管理由MPU分配给DSP的任务。 首先，搜索DSP的空闲处理单元，然后将任务的多个线程中的一个分配给处理单元。 最后，处理单元被激活以执行线程。 因此，可以有效地提高多核处理器的通信效率，同时可以节省硬件成本。

公开(公告)号：US08972471B2

公开(公告)日：2015-03-03

申请号：US13611146

申请日：2012-09-12

申请人： Chih-Wei Liu ,  Kuo-Chiang Chang ,  Shih-Hao Ou ,  Yu-Wen Chen

发明人： Chih-Wei Liu ,  Kuo-Chiang Chang ,  Shih-Hao Ou ,  Yu-Wen Chen

IPC分类号： G06F7/483

CPC分类号： G06F7/527

摘要： An arithmetic module is provided, including a first adder, a first shifter coupled to the first adder, a multiplier coupled to the first shifter for receiving an external coefficient signal, a digit alignment unit coupled to the multiplier, a second adder coupled to the digit alignment unit, and a second shifter coupled to the second adder. The arithmetic module reduces the overall computation time effectively, as compared with a scalar processor, by employing a serial data connection design, and also significantly reduces power consumption of the digital signal processor by requiring fewer input and output ends than those of a multi-issue processor.

摘要翻译： 提供了一种算术模块，包括第一加法器，耦合到第一加法器的第一移位器，耦合到第一移位器的乘法器，用于接收外部系数信号，耦合到乘法器的数字对准单元，耦合到数字的第二加法器 对准单元和耦合到第二加法器的第二移位器。 与标量处理器相比，算术模块通过采用串行数据连接设计，有效地减少了总体计算时间，并且通过要求比多问题的输入和输出端要求更少的输入和输出端，还可显着降低数字信号处理器的功耗 处理器。

公开(公告)号：US07406588B2

公开(公告)日：2008-07-29

申请号：US11229616

申请日：2005-09-20

申请人： Tay-Jyi Lin ,  Chein-Wei Jen ,  Chih-Wei Liu ,  Po-Han Huang ,  Wei-Sheng Huang ,  Chan-Hao Chang

发明人： Tay-Jyi Lin ,  Chein-Wei Jen ,  Chih-Wei Liu ,  Po-Han Huang ,  Wei-Sheng Huang ,  Chan-Hao Chang

IPC分类号： G06F9/38

CPC分类号： G06F9/3869

摘要： A pipelined datapath with dynamically reconfigurable pipeline stages is provided, having a pipeline controller which generates clock signals and selects signals based on a system clock and a valid data signal to control each of the registers and each of the multiplexers in the pipeline circuit. In other words, when a valid datum is being processed, the pipeline register is activated to latch the output of the combinational logic circuit; otherwise, when an invalid datum is received, the register is not activated and the datum bypasses the register through a multiplexer. Therefore, the pipeline stages of the pipelined datapath are dynamically reconfigured to save the power dissipation effectively.

摘要翻译： 提供了具有动态可重构流水线级的流水线数据路径，具有管线控制器，其生成时钟信号并基于系统时钟和有效数据信号选择信号，以控制流水线电路中的每个寄存器和多路复用器。 换句话说，当正在处理有效数据时，激活流水线寄存器来锁存组合逻辑电路的输出; 否则，当接收到无效数据时，寄存器不被激活，并且基准通过多路复用器旁路寄存器。 因此，流水线数据路径的流水线级可动态重新配置，有效节省功耗。

公开(公告)号：US20060259748A1

公开(公告)日：2006-11-16

申请号：US11229616

申请日：2005-09-20

申请人： Tay-Jyi Lin ,  Chein-Wei Jen ,  Chih-Wei Liu ,  Po-Han Huang ,  Wei-Sheng Huang ,  Chan-Hao Chang

发明人： Tay-Jyi Lin ,  Chein-Wei Jen ,  Chih-Wei Liu ,  Po-Han Huang ,  Wei-Sheng Huang ,  Chan-Hao Chang

IPC分类号： G06F9/44

CPC分类号： G06F9/3869

摘要： A pipelined datapath with dynamically reconfigurable pipeline stages is provided, having a pipeline controller which generates clock signals and selects signals based on a system clock and a valid data signal to control each of the registers and each of the multiplexers in the pipeline circuit. In other words, when a valid datum is being processed, the pipeline register is activated to latch the output of the combinational logic circuit; otherwise, when an invalid datum is received, the register is not activated and the datum bypasses the register through a multiplexer. Therefore, the pipeline stages of the pipelined datapath are dynamically reconfigured to save the power dissipation effectively.

摘要翻译： 提供了具有动态可重构流水线级的流水线数据路径，具有管线控制器，其生成时钟信号并基于系统时钟和有效数据信号选择信号，以控制流水线电路中的每个寄存器和多路复用器。 换句话说，当正在处理有效数据时，激活流水线寄存器来锁存组合逻辑电路的输出; 否则，当接收到无效数据时，寄存器不被激活，并且基准通过多路复用器旁路寄存器。 因此，流水线数据路径的流水线级可动态重新配置，有效节省功耗。

公开(公告)号：US20060212663A1

公开(公告)日：2006-09-21

申请号：US11246115

申请日：2005-10-11

申请人： Tay-Jyi Lin ,  Pi-Chen Hsiao ,  Chih-Wei Liu ,  Chein-Wei Jen ,  I-Tao Liao ,  Po-Han Huang

发明人： Tay-Jyi Lin ,  Pi-Chen Hsiao ,  Chih-Wei Liu ,  Chein-Wei Jen ,  I-Tao Liao ,  Po-Han Huang

IPC分类号： G06F12/00

CPC分类号： G06F15/173

摘要： An inter-cluster communication module using the memory access network is provided, including a plurality of clusters, a memory subsystem, a controller and a switch device. When some clusters issue a load instruction and some clusters issue a store instruction of an identical memory address concurrently, the controller controls the switch device which connects the clusters and the memory banks of the memory subsystem, so that the data item is transmitted from the cluster issuing the store instruction to the cluster issuing the load instruction through the switch device, thereby achieving data exchange between the clusters. Herein, the data item is selectively stored in the memory module depending on the address. Furthermore, the data item is also transmitted between the memory and the clusters over the switch device.

摘要翻译： 提供了使用存储器访问网络的集群间通信模块，包括多个集群，存储器子系统，控制器和交换设备。 当一些集群发出加载指令并且一些集群同时发出相同存储器地址的存储指令时，控制器控制连接存储器子系统的集群和存储器组的交换设备，从而从集群发送数据项 通过交换设备向发布加载指令的集群发出存储指令，由此实现集群之间的数据交换。 这里，数据项根据地址被选择性地存储在存储器模块中。 此外，数据项也通过交换设备在存储器和簇之间传输。

公开(公告)号：US20080162870A1

公开(公告)日：2008-07-03

申请号：US11780480

申请日：2007-07-20

申请人： Tay-Jyi Lin ,  Chein-Wei Jen ,  Pi-Chen Hsiao ,  Li-Chun Lin ,  Chih-Wei Liu

发明人： Tay-Jyi Lin ,  Chein-Wei Jen ,  Pi-Chen Hsiao ,  Li-Chun Lin ,  Chih-Wei Liu

IPC分类号： G06F15/00

CPC分类号： G06F9/3824 ,  G06F9/3828 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3891

摘要： Disclosed is a virtual cluster architecture and method. The virtual cluster architecture includes N virtual clusters, N register files, M sets of function units, a virtual cluster control switch, and an inter-cluster communication mechanism. This invention uses a way of time sharing or time multiplexing to alternatively execute a single program thread across multiple parallel clusters. It minimizes the hardware resources for complicated forwarding circuitry or bypassing mechanism by greatly increasing the tolerance of instruction latency in the datapath. This invention may distribute function units serially into pipeline stages to support composite instructions. The performance and the code sizes of application programs can therefore be significantly improved with these composite instructions, of which the introduced latency can be completely hidden in this invention. This invention also has the advantage of being compatible with the program codes developed on conventional multi-cluster architectures.

摘要翻译： 公开了一种虚拟集群架构和方法。 虚拟集群架构包括N个虚拟集群，N个寄存器文件，M个功能单元组，一个虚拟集群控制交换机和一个集群间通信机制。 本发明使用时间共享或时间复用的方式来交替地在多个并行簇上执行单个程序线程。 它通过大大增加数据路径中指令延迟的容限，最大限度地减少了复杂转发电路或旁路机制的硬件资源。 本发明可以将功能单元串行地分配到流水线阶段以支持复合指令。 因此，通过这些复合指令可以显着改善应用程序的性能和代码大小，其中引入的延迟可以完全隐藏在本发明中。 本发明还具有与常规多集群架构上开发的程序代码兼容的优点。

公开(公告)号：US20060236079A1

公开(公告)日：2006-10-19

申请号：US11297395

申请日：2005-12-09

申请人： Tay-Jyi Lin ,  Chein-Wei Jen ,  Chia-Hsien Liu ,  Chih-Wei Liu ,  I-Tao Liao ,  Po-Han Huang

发明人： Tay-Jyi Lin ,  Chein-Wei Jen ,  Chia-Hsien Liu ,  Chih-Wei Liu ,  I-Tao Liao ,  Po-Han Huang

IPC分类号： G06F9/44

CPC分类号： G06F9/30145 ,  G06F9/3012 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3885 ,  G06F9/3891

摘要： A unified single-core and multi-mode processor and its program execution method are provided. In an embodiment of this processor, a single instruction stream is different types of instructions randomly arranged in thereof. The processor switches its modes based on the type of a fetched instruction to execute the program corresponding to the fetched instruction.

摘要翻译： 提供统一的单核和多模式处理器及其程序执行方法。 在该处理器的一个实施例中，单个指令流是随机布置在其中的不同类型的指令。 处理器根据获取的指令的类型切换其模式，以执行与获取的指令相对应的程序。

公开(公告)号：US07950840B2

公开(公告)日：2011-05-31

申请号：US12417133

申请日：2009-04-02

申请人： Chun-Ming Liu ,  Uei-Shin Chen ,  Chih-Wei Liu

发明人： Chun-Ming Liu ,  Uei-Shin Chen ,  Chih-Wei Liu

IPC分类号： H01R33/00

CPC分类号： H01R33/09 ,  F21V19/0005 ,  F21Y2115/10

摘要： A structure for LED Christmas light is provided, including a light holder, being a hollow body having a separating part connected to the inner wall of the light holder to divide the hollow interior of the light holder into two cavities. Each of the two opposite sides of the inner wall of the light holder connected to the separating part forms a slot and face the surface of the separating part of the two cavities, with each having a guiding channel. Two wire sets are fixed inside the two cavities. An LED light bulb has a positive pin and a negative pin inserted inside the guiding channel, respectively, and being electrically connected to the wire sets. A light cap has a holding part passing the LED light bulb to tightly engage to the top of the light holder so as to fix the LED light bulb to the light holder.

摘要翻译： 提供了一种用于LED圣诞灯的结构，包括灯座，该灯架是具有连接到灯架的内壁的分离部分的中空本体，以将灯座的中空内部分成两个空腔。 连接到分离部分的灯支架的内壁的两个相对侧中的每一个形成一个狭槽，并且面对两个空腔的分离部分的表面，每个具有引导通道。 两个线组固定在两个腔内。 LED灯泡具有分别插入引导通道内的正极销和负极引脚，并且与导线组电连接。 灯帽具有通过LED灯泡的保持部分，以紧密接合到灯架的顶部，以将LED灯泡固定到灯座上。