公开(公告)号：US20240231669A1

公开(公告)日：2024-07-11

申请号：US18611664

申请日：2024-03-20

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Xiaoping Zhu ,  Huan Chen

IPC: G06F3/06

CPC classification number: G06F3/0647 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0683

Abstract: In a data processing method implemented in a hierarchical memory system including a first memory medium and a second memory medium of different types, a processor obtains data distribution in the hierarchical memory system. The processor determines a data migration manner based on the data distribution, where the data migration manner is for implementing migration processing on a migration data set between the different memory media based on the data distribution. The processor then performs migration processing on the migration data set based on the migration manner.

公开(公告)号：US20240231654A1

公开(公告)日：2024-07-11

申请号：US18612459

申请日：2024-03-21

Applicant: Huawei Technologies Co., Ltd.

Inventor： Huan Chen ,  Xiaoping Zhu

IPC: G06F3/06

CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/0683

Abstract: A method for controlling an internal memory bandwidth includes after obtaining a bandwidth required by a to-be-accessed internal memory medium, a processor in a system obtains an occupancy rate of an internal memory bandwidth of the to-be-accessed internal memory medium. If determining, based on the occupancy rate of the internal memory bandwidth, that the to-be-accessed internal memory medium cannot satisfy a bandwidth requirement, the processor adjusts, under an indication of a bandwidth adjustment policy, the occupancy rate of the internal memory bandwidth based on a factor that affects the occupancy rate of the internal memory bandwidth of the to-be-accessed internal memory medium, and the processor uses a first bandwidth that satisfies the bandwidth requirement in an adjusted remaining bandwidth of the to-be-accessed internal memory medium.

公开(公告)号：US20240231653A1

公开(公告)日：2024-07-11

申请号：US18611674

申请日：2024-03-20

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Huan Chen ,  Xiaoping Zhu ,  Zeyao He

IPC: G06F3/06

CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/0679

Abstract: In a memory management method, a first processor in a system is associated with at least two different types of memory media. After obtaining a memory allocation request, the first processor fully considers physical attributes such as a memory capacity, an access latency, a cost, or a service life of the multiple different types of memory media in the system when allocating a memory resource to a running application. The processor selects a to-be-allocated memory resource from the multiple different types of memory media based on a low access latency of the first processor accessing an allocated memory resource.

公开(公告)号：US20240113501A1

公开(公告)日：2024-04-04

申请号：US18533874

申请日：2023-12-08

Applicant: Huawei Technologies Co., Ltd.

Inventor： Zhiyuan Lin ,  Huan Chen ,  Gang Li ,  Xiaofan Wu ,  Xiaolu Song

IPC: H01S5/042 ,  H04B10/564

CPC classification number: H01S5/042 ,  H04B10/564

Abstract: An optoelectrical assembly includes a voltage conversion circuit, an optoelectrical semiconductor device, an optoelectrical detection circuit, and a controller. The voltage conversion circuit provides a bias voltage to the optoelectrical semiconductor device, and adjusts, by changing the bias voltage, an output optical power. A differential resistance value (Rdiff) of the optoelectrical semiconductor device within a range of a target optical power satisfies 0.1 ohm (Ω)≤Rdiff≤50Ω, and the differential resistance value is a ratio of a voltage variation to a current variation corresponding to the voltage variation. The optoelectrical detection circuit detects the output optical power, and outputs a detection signal to the controller. The controller determines a control signal based on the detection signal, and outputs the control signal to the voltage conversion circuit, where the control signal is used to adjust the bias voltage.