MEMORY MANAGEMENT METHOD AND APPARATUS, PROCESSOR, AND COMPUTING DEVICE

    公开(公告)号:US20240231653A1

    公开(公告)日:2024-07-11

    申请号:US18611674

    申请日:2024-03-20

    CPC classification number: G06F3/0631 G06F3/0604 G06F3/0679

    Abstract: In a memory management method, a first processor in a system is associated with at least two different types of memory media. After obtaining a memory allocation request, the first processor fully considers physical attributes such as a memory capacity, an access latency, a cost, or a service life of the multiple different types of memory media in the system when allocating a memory resource to a running application. The processor selects a to-be-allocated memory resource from the multiple different types of memory media based on a low access latency of the first processor accessing an allocated memory resource.

    DATA PROCESSING METHOD AND APPARATUS, PROCESSOR, AND HYBRID MEMORY SYSTEM

    公开(公告)号:US20240231669A1

    公开(公告)日:2024-07-11

    申请号:US18611664

    申请日:2024-03-20

    CPC classification number: G06F3/0647 G06F3/0604 G06F3/0653 G06F3/0683

    Abstract: In a data processing method implemented in a hierarchical memory system including a first memory medium and a second memory medium of different types, a processor obtains data distribution in the hierarchical memory system. The processor determines a data migration manner based on the data distribution, where the data migration manner is for implementing migration processing on a migration data set between the different memory media based on the data distribution. The processor then performs migration processing on the migration data set based on the migration manner.

    Method and Apparatus for Controlling Internal Memory Bandwidth, Processor, and Computing Device

    公开(公告)号:US20240231654A1

    公开(公告)日:2024-07-11

    申请号:US18612459

    申请日:2024-03-21

    CPC classification number: G06F3/0631 G06F3/0604 G06F3/0683

    Abstract: A method for controlling an internal memory bandwidth includes after obtaining a bandwidth required by a to-be-accessed internal memory medium, a processor in a system obtains an occupancy rate of an internal memory bandwidth of the to-be-accessed internal memory medium. If determining, based on the occupancy rate of the internal memory bandwidth, that the to-be-accessed internal memory medium cannot satisfy a bandwidth requirement, the processor adjusts, under an indication of a bandwidth adjustment policy, the occupancy rate of the internal memory bandwidth based on a factor that affects the occupancy rate of the internal memory bandwidth of the to-be-accessed internal memory medium, and the processor uses a first bandwidth that satisfies the bandwidth requirement in an adjusted remaining bandwidth of the to-be-accessed internal memory medium.

    Hot plug method, host controller, host, and PCIE bridge device

    公开(公告)号:US10423560B2

    公开(公告)日:2019-09-24

    申请号:US15859758

    申请日:2018-01-02

    Abstract: A hot plug method, a host controller, a host, and a PCIe bridge device. The method includes: generating, by a host controller, a first notification packet, where the first notification packet includes hot plug interruption information, and the hot plug interruption information indicates that a first PCIe device is to be hot-plugged; sending, by the host controller, the first notification packet to a host, so that the host performs, according to the first notification packet, a hot plug operation corresponding to the PCIe device; and receiving, by the host controller, a second notification packet sent by the host, and sending the second notification packet to a user equipment controller, to facilitate the user equipment controller to instruct a user to insert or remove the PCIe device, where the second notification packet is for indicating that the hot plug operation corresponding to the PCIe device is completed.

    HOT PLUG METHOD, HOST CONTROLLER, HOST, AND PCIE BRIDGE DEVICE

    公开(公告)号:US20180121383A1

    公开(公告)日:2018-05-03

    申请号:US15859758

    申请日:2018-01-02

    Abstract: A hot plug method, a host controller, a host, and a PCIe bridge device. The method includes: generating, by a host controller, a first notification packet, where the first notification packet includes hot plug interruption information, and the hot plug interruption information indicates that a first PCIe device is to be hot-plugged; sending, by the host controller, the first notification packet to a host, so that the host performs, according to the first notification packet, a hot plug operation corresponding to the PCIe device; and receiving, by the host controller, a second notification packet sent by the host, and sending the second notification packet to a user equipment controller, to facilitate the user equipment controller to instruct a user to insert or remove the PCIe device, where the second notification packet is for indicating that the hot plug operation corresponding to the PCIe device is completed.

Patent Agency Ranking