公开(公告)号：US11508423B2

公开(公告)日：2022-11-22

申请号：US16913576

申请日：2020-06-26

Applicant: Huawei Technologies Co., Ltd.

Inventor： Youming Tsao ,  Bingwu Ji ,  Cong Yao ,  Jiahua Lin

IPC: G11C7/24 ,  G06F1/3287 ,  G11C5/14 ,  G11C7/10

Abstract: A chip includes a processor, a memory, and a storage controller of the memory. There is an access path between the processor and the storage controller, and the processor reads data from or writes data into the memory by using the storage controller through the access path. The chip further includes a shielding circuit. The shielding circuit is configured to shield a signal on the access path when the processor is powered off.

公开(公告)号：US20180364791A1

公开(公告)日：2018-12-20

申请号：US16116352

申请日：2018-08-29

Applicant: Huawei Technologies Co., Ltd.

Inventor： Youming Tsao ,  Cong Yao

IPC: G06F1/32 ,  G06F1/08 ,  G06F11/30

Abstract: The present disclosure provides a control system and a control method for a double data rate synchronous dynamic random access memory (DDR) system in order to reduce power consumption of the DDR system. The system includes a memory and a processor coupled to the memory, and the processor is configured to monitor a working status of each functional system that shares a power domain with the DDR system, determine a target power parameter value and a target clock parameter value of the DDR system according to the working status of each functional system, and control a power parameter and a clock parameter of the DDR system according to the target power parameter value and the target clock parameter value of the DDR system.

公开(公告)号：US10915158B2

公开(公告)日：2021-02-09

申请号：US16116352

申请日：2018-08-29

Applicant: Huawei Technologies Co., Ltd.

Inventor： Youming Tsao ,  Cong Yao

IPC: G06F1/00 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/32 ,  G06F1/3225 ,  G11C11/4074 ,  G11C7/10 ,  G06F1/3206 ,  G06F1/3296 ,  G06F1/08 ,  G06F11/30

Abstract: The present disclosure provides a control system and a control method for a double data rate synchronous dynamic random access memory (DDR) system in order to reduce power consumption of the DDR system. The system includes a memory and a processor coupled to the memory, and the processor is configured to monitor a working status of each functional system that shares a power domain with the DDR system, determine a target power parameter value and a target clock parameter value of the DDR system according to the working status of each functional system, and control a power parameter and a clock parameter of the DDR system according to the target power parameter value and the target clock parameter value of the DDR system.

公开(公告)号：US20200327915A1

公开(公告)日：2020-10-15

申请号：US16913576

申请日：2020-06-26

Applicant: Huawei Technologies Co., Ltd.

Inventor： Youming Tsao ,  Bingwu Ji ,  Cong Yao ,  Jiahua Lin

IPC: G11C7/24 ,  G06F1/3287 ,  G11C5/14

Abstract: A chip includes a processor, a memory, and a storage controller of the memory. There is an access path between the processor and the storage controller, and the processor reads data from or writes data into the memory by using the storage controller through the access path. The chip further includes a shielding circuit. The shielding circuit is configured to shield a signal on the access path when the processor is powered off.