Abstract:
A process for fabricating a field effect transistor having minimal parasitic inversion wherein a field layer of insulating material is formed on a monocrystalline substrate having spaced source and drain regions, an opening formed in the field layer over the gate region, and the body bombarded with impurity ions of the same type as the background doping of the semiconductor body, the bombarding done at an energy sufficient to traverse the field insulation layer to produce an increased concentration of impurity ions just beneath the interface of the semiconductor body and field oxide, and a buried layer of impurity in the gate region.
Abstract:
The invention is concerned with methods for producing improved semiconductor devices. The invention is advantageously employable in the fabrication of insulated-gate field-effect transistor devices. The problem of accurately aligning the gate electrode over the channel region, lying between the source region and the drain region of a field effect transistor, is particularly addressed and solved. Accurate and precise field protection of all areas of the field-effect transistor surrounding the channel, source and drain regions is simply and effectively accomplished. The proper alignment of the gate electrode is largely accomplished by utilizing essentially the same mask structure to define the gate, source and drain regions. The same mask structure is utilized to define the area that is field protected.