公开(公告)号：US3648246A

公开(公告)日：1972-03-07

申请号：US3648246D

申请日：1970-04-16

Applicant: IBM

Inventor： ZURLA FRANK A

IPC: G06F7/494 ,  G06F7/50 ,  G06F7/38

CPC classification number: G06F7/494 ,  G06F2207/3828 ,  G06F2207/4924

Abstract: The present improvement makes use of a high-speed microprogrammed processor which has means for selecting the time duration of each basic machine cycle as the current control word is being executed. During a decimal add operation, the decimal operands are processed as normal binary values and the result is processed a second time in the binary adder to correct the result if necessary. The two ALU (arithmetic and logic unit) steps are executed during one machine cycle which is slightly longer than a normal binary add (or prior art decimal add) cycle; however, this arrangement improves overall processor performance by removing a stage of delay from the ALU input for all ALU operations. In addition, decimal error checking savings are effected.

Abstract translation: 目前的改进是利用高速微程序处理器，其具有当正在执行当前控制字时选择每个基本机器周期的持续时间的装置。 在十进制加法操作期间，十进制操作数作为普通二进制值进行处理，并在二进制加法器中再次处理结果，以便在需要时更正结果。 在一个机器周期中执行两个ALU（算术和逻辑单元）步骤，其比常规二进制加法（或现有技术十进制加法）周期稍长; 然而，这种布置通过从所有ALU操作的ALU输入中消除延迟阶段来提高整体处理器性能。 另外，进行十进制错误检查节省。

公开(公告)号：US3656123A

公开(公告)日：1972-04-11

申请号：US3656123D

申请日：1970-04-16

Applicant: IBM

Inventor： CARNEVALE RICHARD J ,  HOWE LELAND D JR ,  METZ THOMAS A ,  WOMACK KARL K ,  ZURLA FRANK A

IPC: G06F9/22 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/12

CPC classification number: G06F9/30192 ,  G06F9/223 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3869

Abstract: A microprogrammed processor has a single storage unit for both main store and control store wherein the read/write times of the storage unit are less than the time required for the microprogram controlled hardware to execute a control word. Since there is no requirement for the hardware to wait for a next succeeding access to storage as in typical known processors, but rather the storage unit now waits for the hardware, it becomes feasible and practicable to improve the performance of the processor significantly with little additional cost by providing basic machine cycle times for different control word executions which are maintained at a minimum. In the preferred embodiment, a decode circuit examines each control word after it is transferred from control store to a control register to determine the word type which is to be executed. Depending upon the word type, the decode circuitry applies control pulses to the processor clock to cause ti to produce a selected one of three available cycle lengths or a combination of two of said three available cycle lengths. In this manner, system performance is significantly improved.

Abstract translation: 微程序处理器具有用于主存储和控制存储的单个存储单元，其中存储单元的读/写时间小于微程序控制的硬件执行控制字所需的时间。 由于硬件不需要像在典型的已知处理器中等待下一次成功访问存储，而是存储单元现在等待硬件，因此显着地提高处理器的性能变得可行和可行 通过为保持最小的不同控制字执行提供基本的机器周期时间来降低成本。 在优选实施例中，解码电路在从控制存储器传送到控制寄存器之后检查每个控制字以确定要被执行的字类型。 根据字类型，解码电路将控制脉冲施加到处理器时钟以使得ti产生三个可用周期长度中选择的一个或所述三个可用周期长度中的两个的组合。 以这种方式，系统性能得到显着改善。