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    Microprogrammed processor with variable basic machine cycle lengths
    5.
    发明授权
    Microprogrammed processor with variable basic machine cycle lengths 失效
    具有可变基本机器循环长度的微处理器

    公开(公告)号：US3656123A

    公开(公告)日：1972-04-11

    申请号：US3656123D

    申请日：1970-04-16

    Applicant: IBM

    Inventor： CARNEVALE RICHARD J ,  HOWE LELAND D JR ,  METZ THOMAS A ,  WOMACK KARL K ,  ZURLA FRANK A

    IPC: G06F9/22 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/12

    CPC classification number: G06F9/30192 ,  G06F9/223 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3869

    Abstract: A microprogrammed processor has a single storage unit for both main store and control store wherein the read/write times of the storage unit are less than the time required for the microprogram controlled hardware to execute a control word. Since there is no requirement for the hardware to wait for a next succeeding access to storage as in typical known processors, but rather the storage unit now waits for the hardware, it becomes feasible and practicable to improve the performance of the processor significantly with little additional cost by providing basic machine cycle times for different control word executions which are maintained at a minimum. In the preferred embodiment, a decode circuit examines each control word after it is transferred from control store to a control register to determine the word type which is to be executed. Depending upon the word type, the decode circuitry applies control pulses to the processor clock to cause ti to produce a selected one of three available cycle lengths or a combination of two of said three available cycle lengths. In this manner, system performance is significantly improved.

    Abstract translation: 微程序处理器具有用于主存储和控制存储的单个存储单元，其中存储单元的读/写时间小于微程序控制的硬件执行控制字所需的时间。 由于硬件不需要像在典型的已知处理器中等待下一次成功访问存储，而是存储单元现在等待硬件，因此显着地提高处理器的性能变得可行和可行 通过为保持最小的不同控制字执行提供基本的机器周期时间来降低成本。 在优选实施例中，解码电路在从控制存储器传送到控制寄存器之后检查每个控制字以确定要被执行的字类型。 根据字类型，解码电路将控制脉冲施加到处理器时钟以使得ti产生三个可用周期长度中选择的一个或所述三个可用周期长度中的两个的组合。 以这种方式，系统性能得到显着改善。

    Data processing system
    6.
    发明授权
    Data processing system 失效

    公开(公告)号：US3400371A

    公开(公告)日：1968-09-03

    申请号：US35737264

    申请日：1964-04-06

    Applicant: IBM

    Inventor： AMDAHL GENE M ,  BLAAUW GERRIT A ,  MAGDALL ALBERT A ,  PERKINS JR CHARLES B ,  ROOD JOHN W ,  UPDIKE BRUCE M ,  VILLANTE ANTHONY E ,  HELMUT WEBER ,  BOEHM ELAINE M ,  PETER CALINGAERT ,  CARNEVALE RICHARD J ,  PAUL CASE RICHARD ,  COLLINS ARTHUR F ,  GREENE JACK E ,  HANF WILLIAM P ,  JOHNSON JACOB R

    IPC: G06F3/00 ,  G06F3/06 ,  G06F3/12 ,  G06F7/38 ,  G06F7/50 ,  G06F7/575 ,  G06F9/22 ,  G06F9/26 ,  G06F9/30 ,  G06F9/302 ,  G06F9/32 ,  G06F9/46 ,  G06F11/16 ,  G06F12/14 ,  G06F13/00 ,  G06F13/12 ,  G06F13/22 ,  G06F13/26 ,  G06F13/38 ,  G06F15/78 ,  G06F17/21

    CPC classification number: G06F7/575 ,  G06F3/00 ,  G06F3/06 ,  G06F3/12 ,  G06F7/38 ,  G06F7/50 ,  G06F9/226 ,  G06F9/26 ,  G06F9/264 ,  G06F9/30 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30058 ,  G06F9/30094 ,  G06F9/30167 ,  G06F9/46 ,  G06F11/1641 ,  G06F12/1466 ,  G06F13/00 ,  G06F13/122 ,  G06F13/22 ,  G06F13/26 ,  G06F13/38 ,  G06F15/78 ,  G06F17/21 ,  G06F2207/3856

    Abstract: 1,061,361. Editing data. INTERNATIONAL BUSINESS MACHINES CORPORATION. Feb. 11, 1965 [April 6, 1964], No. 5906/65. Heading G4A. In an electronic data processing system, data characters to be edited are transferred selectively and successively under partial control of a bi-stable device from a first (" source ") storage field to a second (" pattern ") storage field initially containing control and data characters (e.g. decimal point), whereby at the conclusion of an editing operation the second field contains selected characters from the first field selectively interspersed with data characters of the second field. Bytes each have 8 bits and comprise two binary-coded decimal digits or one such and a sign (" packed " format), or one such digit plus 4 zone bits (" unpacked " format). Provision is made for interchanging the two halves of a byte in a register to simplify test on a half, testing being done generally by subtracting a constant from the number and seeing if the result is zero. The bi-stable device referred to above is a " significance trigger " which is 0 if the next " source " character is presumed non-significant and 1 if significant. The trigger is set to 1 if the " source " character is non-zero, or when a " significance start " control character is detected in the " pattern " field, and set to 0 when a " field separation " control character is detected. The characters of the " pattern " field are accessed from memory in turn. Those not control characters are retained in the " pattern " field if the "significance trigger " is at 1 but replaced by fill characters if at .0. " Field separation " control characters are replaced by fill characters. Detection of a " significance start " control character or a " digit select " control character results in the accessing of the. corresponding " source " character. If this is non-zero or if the "significance trigger " is at 1, it replaces the control character in the "pattern " field after being " unpacked " by insertion of zone bits 1111. Otherwise the control character is replaced by a fill character. The editing operation is initiated by an instruction word containing an OP code specifying either normal, editing as above or the latter plus the additional feature of storing the address in the "pattern " field of the highest significant character in the "source" field when this is detected through switching of the " significance trigger ". This facilitates later insertion of e.g. a currency symbol. The editing instruction word also specifies the number of bytes in the " pattern " field and the addresses of the highest order bytes of the " source " and " pattern " fields. These addresses are each specified by specifying a number and a register, the contents of the register being added to the number to get the address. Detection of a sign character in the " source " field sets to 1 a trigger to indicate that a sign is present, and if the sign is negative sets a further trigger to 1 to indicate this. This will cause the " significance trigger " to be set to 1. The second sign trigger and another trigger set to 1 in the presence of a non-zero " source " digit can be used to control subsequent (unspecified) operations. Reference has been directed by the Comptroller to Specification 954,801.

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