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    Address modification by main/control store boundary register in a microprogrammed processor
    1.
    发明授权
    Address modification by main/control store boundary register in a microprogrammed processor 失效
    微处理器主控/存储边界寄存器的地址修改

    公开(公告)号：US3651475A

    公开(公告)日：1972-03-21

    申请号：US3651475D

    申请日：1970-04-16

    Applicant: IBM

    Inventor： DUNBAR ROBERT G JR ,  WOMACK KARL K

    IPC: G06F12/06 ,  G06F9/20

    CPC classification number: G06F12/0623

    Abstract: An address check boundary (ACB) register is initialized in accordance with the total amount of control/main storage with common addressing and with the relative amounts of control and main storage for the purpose of: 1. PROVIDING THE HIGHER ORDER BITS OF CONTROL STORE ADDRESS THUS PERMITTING FEWER BITS IN THE MICROPROGRAM SUPPLIED CONTROL STORE ADDRESS WITH RESULTING REDUCTION IN THE CONTROL WORD SIZE; 2. MODIFYING THE ACB supplied higher order bits and/or the microprogram supplied address bits where required; 3. SUPPLYING THE BOUNDARY ADDRESS BETWEEN CONTROL/MAIN STORE TO INITIATE AN ERROR SIGNAL IF MAIN STORE IS ACCESSED WHEN CONTROL STORE SHOULD HAVE BEEN ACCESSED AND VICE VERSA; 4. PROVIDING DATA REGARDING THE TYPE (INTERNAL - EXTERNAL) AND AMOUNT OF MAIN STORAGE AND REGARDING THE SYSTEM TYPE - SIMPLEX (ONE PROCESSOR) OR DUPLEX (TWO PROCESSORS).

    Abstract translation: 地址检查边界（ACB）寄存器根据具有共同寻址的控制/主存储总量以及相对控制量和主存储量进行初始化，目的是：

    Processor with improved controls for selecting an operand from a local storage unit, an alu output register or both
    2.
    发明授权
    Processor with improved controls for selecting an operand from a local storage unit, an alu output register or both 失效
    具有改进的用于从本地存储单元选择操作的控制器的处理器，ALU输出寄存器或两个

    公开(公告)号：US3651476A

    公开(公告)日：1972-03-21

    申请号：US3651476D

    申请日：1970-04-16

    Applicant: IBM

    Inventor： METZ THOMAS A ,  WOMACK KARL K

    IPC: G06F9/38 ,  G06F13/16 ,  G06F7/38

    CPC classification number: G06F9/3824 ,  G06F13/16

    Abstract: In a high performance microprogrammed processor, ALU results obtained during one microprogram cycle are destined to a pair of high speed local storage units during the next succeeding cycle. During each write operation, identical data is stored in corresponding register positions of each local storage unit. This permits simultaneous accessing of any two operands from the local storage units during read operations for application to ALU input registers. Means are effective early in each cycle for comparing the operand addresses with the destination address of ALU results (if any) from the next preceding cycle. If one of the operand addresses equals the destination address, only that portion (one to four bytes) of the local store operand data, which is not updated due to the results not being destined, is blocked from entry to the ALU input register; and, instead, the corresponding ALU results are gated directly to the appropriate ALU input register for processing. Later in the cycle the ALU results are also destined to the register positions of both local storage units corresponding to the destination address.

    Abstract translation: 在高性能微程序处理器中，在一个微程序循环期间获得的ALU结果将在下一个后续循环期间注定为一对高速本地存储单元。 在每次写入操作期间，相同的数据被存储在每个本地存储单元的对应的寄存器位置中。 这允许在读操作期间从本地存储单元同时访问任何两个操作数，以应用于ALU输入寄存器。 手段在每个周期的早期有效，用于将操作数地址与下一个前一周期的ALU结果（如果有的话）的目标地址进行比较。 如果其中一个操作数地址等于目的地址，则只有本地存储操作数数据（由于结果未发送而未更新）的部分（1到4个字节）被阻止进入ALU输入寄存器; 而相应的ALU结果直接门控到适当的ALU输入寄存器进行处理。 在周期中，ALU结果也将注定到与目标地址对应的两个本地存储单元的寄存器位置。

    Microprogrammed processor with variable basic machine cycle lengths
    5.
    发明授权
    Microprogrammed processor with variable basic machine cycle lengths 失效
    具有可变基本机器循环长度的微处理器

    公开(公告)号：US3656123A

    公开(公告)日：1972-04-11

    申请号：US3656123D

    申请日：1970-04-16

    Applicant: IBM

    Inventor： CARNEVALE RICHARD J ,  HOWE LELAND D JR ,  METZ THOMAS A ,  WOMACK KARL K ,  ZURLA FRANK A

    IPC: G06F9/22 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/12

    CPC classification number: G06F9/30192 ,  G06F9/223 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3869

    Abstract: A microprogrammed processor has a single storage unit for both main store and control store wherein the read/write times of the storage unit are less than the time required for the microprogram controlled hardware to execute a control word. Since there is no requirement for the hardware to wait for a next succeeding access to storage as in typical known processors, but rather the storage unit now waits for the hardware, it becomes feasible and practicable to improve the performance of the processor significantly with little additional cost by providing basic machine cycle times for different control word executions which are maintained at a minimum. In the preferred embodiment, a decode circuit examines each control word after it is transferred from control store to a control register to determine the word type which is to be executed. Depending upon the word type, the decode circuitry applies control pulses to the processor clock to cause ti to produce a selected one of three available cycle lengths or a combination of two of said three available cycle lengths. In this manner, system performance is significantly improved.

    Abstract translation: 微程序处理器具有用于主存储和控制存储的单个存储单元，其中存储单元的读/写时间小于微程序控制的硬件执行控制字所需的时间。 由于硬件不需要像在典型的已知处理器中等待下一次成功访问存储，而是存储单元现在等待硬件，因此显着地提高处理器的性能变得可行和可行 通过为保持最小的不同控制字执行提供基本的机器周期时间来降低成本。 在优选实施例中，解码电路在从控制存储器传送到控制寄存器之后检查每个控制字以确定要被执行的字类型。 根据字类型，解码电路将控制脉冲施加到处理器时钟以使得ti产生三个可用周期长度中选择的一个或所述三个可用周期长度中的两个的组合。 以这种方式，系统性能得到显着改善。

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