公开(公告)号：US20230197528A1

公开(公告)日：2023-06-22

申请号：US18054228

申请日：2022-11-10

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Dunja Radisic ,  Bilal Chehab

IPC: H01L21/8238 ,  H01L27/092 ,  H01L23/522

CPC classification number: H01L21/823871 ,  H01L27/092 ,  H01L23/5226

Abstract: A method for forming an integrated circuit. The method includes providing a semiconductor structure comprising: (i) two transistors, (ii) a gate on the channel of the transistor, (iii) contacts coupled to each transistor, (iv) a dielectric layer over the two transistors, the gate, and the contacts, (v) a first conductive line arranged within a first metallization level and extending along a first direction, (vi) a first conductive via connecting the first conductive line with a first contact of a transistor, and (vii) a second conductive via connecting the first conductive line with a second contact of a transistor. The method also includes recessing the first dielectric layer, providing spacers along the first conductive line, depositing a second dielectric layer on the first dielectric layer, forming an opening in the second dielectric layer and first dielectric layer, and providing a conductive material in the opening, thereby forming a third conductive via.

公开(公告)号：US20210126108A1

公开(公告)日：2021-04-29

申请号：US17083125

申请日：2020-10-28

Applicant: IMEC vzw

Inventor： Boon Teik Chan ,  Dunja Radisic ,  Steven Demuynck ,  Efrain Altamirano Sanchez ,  Soon Aik Chew

IPC: H01L29/66 ,  H01L21/768

Abstract: The disclosed technology is related to a method that includes the formation of contact vias for contacting gate electrodes and source (S) or drain (D) electrodes of nano-sized semiconductor transistors formed on a semiconductor wafer. The electrodes are mutually parallel and provided with dielectric gate and S/D plugs on top of the electrodes, and the mutually parallel electrode/plug assemblies are separated by dielectric spacers. The formation of the vias takes place by two separate self-aligned etch processes, the Vint-A etch for forming one or more vias towards one or more S/D electrodes and the Vint-G etch for forming one or more vias towards one or more gate electrodes. According to the disclosed technology, a conformal layer is deposited on the wafer after the first self-aligned etch process, wherein the conformal layer is resistant to the second self-aligned etch process. The conformal layer thereby protects the first contact via during the second self-aligned etch.

公开(公告)号：US11430876B2

公开(公告)日：2022-08-30

申请号：US17083125

申请日：2020-10-28

Applicant: IMEC vzw

Inventor： Boon Teik Chan ,  Dunja Radisic ,  Steven Demuynck ,  Efrain Altamirano Sanchez ,  Soon Aik Chew

IPC: H01L29/66 ,  H01L21/768

Abstract: The disclosed technology is related to a method that includes the formation of contact vias for contacting gate electrodes and source (S) or drain (D) electrodes of nano-sized semiconductor transistors formed on a semiconductor wafer. The electrodes are mutually parallel and provided with dielectric gate and S/D plugs on top of the electrodes, and the mutually parallel electrode/plug assemblies are separated by dielectric spacers. The formation of the vias takes place by two separate self-aligned etch processes, the Vint-A etch for forming one or more vias towards one or more S/D electrodes and the Vint-G etch for forming one or more vias towards one or more gate electrodes. According to the disclosed technology, a conformal layer is deposited on the wafer after the first self-aligned etch process, wherein the conformal layer is resistant to the second self-aligned etch process. The conformal layer thereby protects the first contact via during the second self-aligned etch.

公开(公告)号：US20230197726A1

公开(公告)日：2023-06-22

申请号：US18064508

申请日：2022-12-12

Applicant: IMEC VZW

Inventor： Book Teik Chan ,  Dunja Radisic ,  Anne Vandooren ,  Juergen Boemmels

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/823857 ,  H01L21/823828 ,  H01L29/0673

Abstract: Example embodiments relate to methods for forming a stacked FET device. An example method includes forming a bottom FET device that includes a source, a drain, at least one channel layer between the source and drain, and a bottom gate electrode arranged along the at least one channel layer. The method also includes forming a bonding layer over the bottom FET. Additionally, the method includes forming a top FET device on the bonding layer. Forming the top FET device includes forming a device layer structure. The device layer structure includes at least one channel layer of a channel semiconductor material and a top sacrificial layer of a sacrificial semiconductor material. Further, the method includes replacing the top sacrificial layer with a dummy layer of a dielectric dummy material, forming a gate-to-gate contact trench, depositing gate electrode material, and forming a source and a drain of the top FET device.