公开(公告)号：US20250107199A1

公开(公告)日：2025-03-27

申请号：US18889130

申请日：2024-09-18

Applicant: Imec vzw

Inventor： Boon Teik Chan ,  Gaspard Hiblot ,  Gioele Mirabelli

IPC: H01L29/66 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A method includes forming an isolation structure in a substrate, forming a fin-shaped structure from the substrate, a bottom sacrificial layer, and a stack of layers, forming a dummy gate over a channel region of the fin-shaped structure, forming a recess at a source/drain region of the fin-shaped structure, the source/drain recess extending through the stack of layers and the bottom sacrificial layer, removing the bottom sacrificial layer thereby forming a void, depositing a bottom dielectric insulation layer in the void, extending the recess into the substrate, depositing a plug in the recess, forming an epitaxial structure to form a source/drain feature above the plug in the recess, removing the dummy gate, removing the sacrificial layers in the channel region, forming a replacement metal gate around the channel layers, thinning the substrate, etching the plug to expose the source/drain feature, and forming a source/drain electrical contact at the source/drain feature.

公开(公告)号：US20240204082A1

公开(公告)日：2024-06-20

申请号：US18543933

申请日：2023-12-18

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Boon Teik Chan ,  Shairfe Muhammad Salahuddin ,  Julien Ryckaert ,  Bilal Chehab ,  Hsiao-Hsuan Liu

IPC: H01L29/66 ,  H01L21/306

CPC classification number: H01L29/66545 ,  H01L21/306 ,  H01L29/66439

Abstract: Example embodiments relate to methods for forming a semiconductor device. One example method includes forming a device structure on a substrate, where the device structure includes a device layer stack that includes a bottom device sub-stack that includes at least one bottom channel layer and a top device sub-stack that includes at least one top channel layer, a sacrificial gate structure extending across the device layer stack, and bottom source/drain structures on opposite ends of at least one bottom channel layer. The method also includes forming an opening exposing the top device sub-stack, wherein forming the opening includes etching the sacrificial gate structure, forming a cut through the top device sub-stack by etching back the top device sub-stack from the opening and, subsequent to forming the cut, forming a functional gate stack on the at least one bottom channel layer.

公开(公告)号：US20240154006A1

公开(公告)日：2024-05-09

申请号：US18501331

申请日：2023-11-03

Applicant: IMEC VZW

Inventor： Zheng Tao ,  Boon Teik Chan

IPC: H01L29/40 ,  H01L29/417

CPC classification number: H01L29/401 ,  H01L29/41733 ,  H01L29/41791 ,  H01L23/535

Abstract: The disclosure relates to a method for forming a semiconductor device. The method includes: forming a device structure on a substrate, the device structure including a fin structure including a pair of source/drain bodies and a channel region between the pair of source/drain bodies, the channel region including at least one channel layer, and the device structure further including a gate structure extending across the channel region of the fin structure. The method also includes forming a metal layer over the source/drain bodies, etching the metal layer to define respective source/drain contacts on the source/drain bodies, and depositing an interlayer dielectric layer over the gate structure and the source/drain contacts.

公开(公告)号：US20230178629A1

公开(公告)日：2023-06-08

申请号：US18060945

申请日：2022-12-01

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Geert Hellings ,  Bilal Chehab ,  Julien Ryckaert ,  Naoto Horiguchi

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238

CPC classification number: H01L29/66439 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/775 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66545

Abstract: A method is provided for forming a FET device. The method includes: forming a preliminary device structure comprising a fin structure comprising a layer stack comprising channel layers and non-channel layers alternating the channel layers, and a deposited layer along a first side of the fin structure and a dummy structure along a second side of the fin structure; forming a mask line; forming along a first side of the fin structure a source and drain trench in the deposited layer; forming a set of source and drain cavities in the layer stack, by etching the fin structure from the source trench and the drain trench; forming a source body and a drain body comprising a respective common body portion a set of prongs protruding from the respective common body portion into the source and drain cavities; embedding the mask line in a cover material and removing the mask structure; forming a gate trench by etching the dummy structure; forming a set of gate cavities in the layer stack by etching the fin structure from the gate trench; and forming a gate body comprising a common gate body portion in the gate trench and a set of gate prongs protruding from the common gate body portion into the gate cavities.

公开(公告)号：US11488826B2

公开(公告)日：2022-11-01

申请号：US16931230

申请日：2020-07-16

Applicant: IMEC vzw

Inventor： Boon Teik Chan ,  Yong Kong Siew ,  Juergen Boemmels

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: In one aspect, a method can include forming, by self-aligned multiple patterning, a first pattern of regularly spaced mandrels on a layer to be patterned; forming hard mask spacers on sidewalls of the mandrels, thereby forming a second pattern formed of assemblies comprising a mandrel and hard mask spacers on sidewalls thereof; and etching the second pattern in the layer to be patterned.

公开(公告)号：US20210391526A1

公开(公告)日：2021-12-16

申请号：US17345827

申请日：2021-06-11

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Ruoyu Li ,  Stefan Kubicek ,  Julien Jussot

IPC: H01L39/24 ,  H01L27/18 ,  H01L39/08 ,  H01L39/22

Abstract: A method for processing a semiconductor device with two closely space gates comprises forming a template structure, wherein the template structure includes at least one sub-structure having a dimension less than the CD. The method further comprises forming a gate layer on and around the template structure. Then, the method comprises removing the part of the gate layer formed on the template structure, and patterning the remaining gate layer into a gate structure including the two gates. Further, the method comprises selectively removing the template structure, wherein the spacing between the two gates is formed by the removed sub-structure.

公开(公告)号：US11056376B2

公开(公告)日：2021-07-06

申请号：US16674953

申请日：2019-11-05

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Jean-Francois de Marneffe ,  Daniil Marinov ,  Han Chung Lin ,  Inge Asselberghs

IPC: H01L21/683 ,  H01L21/02 ,  H01L21/78 ,  H01L29/24 ,  H01L29/786

Abstract: In a first aspect, the present disclosure relates to a method for removing an organic sacrificial material from a 2D material, comprising: providing a target substrate having thereon the 2D material and a layer of the organic sacrificial material over the 2D material, infiltrating the organic sacrificial material with a metal or ceramic material, and removing the organic sacrificial material.

公开(公告)号：US10978335B2

公开(公告)日：2021-04-13

申请号：US16563747

申请日：2019-09-06

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Efrain Altamirano Sanchez ,  Ryan Ryoung han Kim

IPC: H01L21/762 ,  H01L29/66 ,  H01L21/763 ,  H01L21/033 ,  H01L29/78

Abstract: A substrate includes on its surface an array of dual stack semiconductor fins, each fin comprising a monocrystalline first portion, a polycrystalline second portion, and a mask third portion. Trenches between the fins are filled with shallow trench isolation (STI) oxide and with polycrystalline material, after which the surface is planarized. Then a second mask is produced on the planarized surface, the second mask defining at least one opening, each defined opening extending across an exposed fin. A thermal oxidation is performed of the polycrystalline material on either side of the exposed fin in each defined opening, thereby producing two oxide strips in each defined opening. Using the second mask and the oxide strips as a mask for self-aligned etching, the material of the exposed dual stack fins is removed and subsequently replaced by an electrically isolating material, thereby creating gate cut structures.

公开(公告)号：US10784158B2

公开(公告)日：2020-09-22

申请号：US16412923

申请日：2019-05-15

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Efrain Altamirano Sanchez

IPC: H01L21/768 ,  H01L21/311

Abstract: A method for forming a cavity in a semiconductor structure and an intermediate structure is provided. The method includes: (a) providing a semiconductor structure comprising: (i) a semiconductor substrate; (ii) a set of line structures on the semiconductor substrate, each line structure having a top surface and sidewalls, the line structures being separated by trenches therebetween, and (iii) an oxygen-containing dielectric material at least partially filling the trenches in-between the line structures, wherein the top surface of at least one of the line structures is at least partially exposed, and wherein the exposed part of the top surface is composed of an oxygen-free dielectric material; (b) forming a layer of TaSix selectively onto the oxygen-free dielectric material with respect to the oxygen-containing dielectric material (c) forming the cavity by selectively removing at least a portion of the oxygen-containing dielectric material with respect to the TaSix.

公开(公告)号：US20170141199A1

公开(公告)日：2017-05-18

申请号：US15345782

申请日：2016-11-08

Applicant: IMEC VZW

Inventor： Steven Demuynck ,  Zheng Tao ,  Boon Teik Chan ,  Liesbeth Witters ,  Marc Schaekers ,  Antony Premkumar Peter ,  Silvia Armini

IPC: H01L29/417 ,  H01L21/311 ,  H01L29/45 ,  H01L29/08 ,  H01L21/768 ,  H01L21/285 ,  H01L21/02 ,  H01L21/3105

CPC classification number: H01L29/41791 ,  H01L21/02115 ,  H01L21/02123 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76886 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating a semiconductor structure is provided. The method includes providing a patterned substrate comprising a semiconductor region and a dielectric region. A conformal layer of a first dielectric material is deposited directly on the patterned substrate. A layer of a sacrificial material is deposited overlying the conformal layer of the first dielectric material. The sacrificial material is patterned, whereby a part of the semiconductor region remains covered by the patterned sacrificial material. A layer of a second dielectric material is deposited on the patterned substrate, thereby completely covering the patterned sacrificial material. A recess is formed in the second dielectric material by completely removing the patterned sacrificial material. The exposed conformal layer of the first dielectric material is removed selectively to the semiconductor region.