公开(公告)号：US20220005768A1

公开(公告)日：2022-01-06

申请号：US17216686

申请日：2021-03-30

Applicant: Industrial Technology Research Institute

Inventor： Jui-Wen Yang ,  Hsin-Cheng Lai ,  Chieh-Wei Feng ,  Tai-Jui Wang ,  Yu-Hua Chung ,  Tzu-Yang Ting

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/64

Abstract: Provided is a semiconductor package structure including a redistribution layer (RDL) structure, a chip, an electronic device and a stress compensation layer. The RDL structure has a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the RDL structure. The electronic device is disposed in the RDL structure, electrically connected to the chip, and includes a dielectric layer disposed therein. The stress compensation layer is disposed in or outside the RDL structure. The dielectric layer provides a first stress between 50 Mpa and 200 Mpa in a first direction perpendicular to the second surface, the stress compensation layer provides a second stress between 50 Mpa and 200 Mpa in a second direction opposite to the first direction, and the difference between the first stress and the second stress does not exceed 60 Mpa.

公开(公告)号：US20190355713A1

公开(公告)日：2019-11-21

申请号：US16183735

申请日：2018-11-08

Applicant: Industrial Technology Research Institute

Inventor： Cheng-Hung Yu ,  Tai-Jui Wang ,  Chieh-Wei Feng ,  Yu-Hua Chung

IPC: H01L27/02 ,  H02H9/04 ,  H01L23/538

Abstract: A system in package structure and an electrostatic discharge protection structure thereof are provided. The electrostatic discharge protection structure includes a redistribution layer and a first transistor array. The redistribution layer has a first electrode and a second electrode. The first transistor array is coupled to a pin end of at least one integrated circuit, the first electrode and the second electrode. The first transistor array has a plurality of transistors. A plurality of first transistors of the transistors are coupled in parallel, and a plurality of second transistors of the transistors are coupled in parallel. The first transistors and the second transistors are configured to be turned on for dissipating an electrostatic discharge current.

公开(公告)号：US11764166B2

公开(公告)日：2023-09-19

申请号：US17216686

申请日：2021-03-30

Applicant: Industrial Technology Research Institute ,  Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jui-Wen Yang ,  Hsin-Cheng Lai ,  Chieh-Wei Feng ,  Tai-Jui Wang ,  Yu-Hua Chung ,  Tzu-Yang Ting

IPC: H01L23/00 ,  H01L23/64 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L23/49822 ,  H01L23/642 ,  H01L24/08 ,  H01L2224/08235

Abstract: Provided is a semiconductor package structure including a redistribution layer (RDL) structure, a chip, an electronic device and a stress compensation layer. The RDL structure has a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the RDL structure. The electronic device is disposed in the RDL structure, electrically connected to the chip, and includes a dielectric layer disposed therein. The stress compensation layer is disposed in or outside the RDL structure. The dielectric layer provides a first stress between 50 Mpa and 200 Mpa in a first direction perpendicular to the second surface, the stress compensation layer provides a second stress between 50 Mpa and 200 Mpa in a second direction opposite to the first direction, and the difference between the first stress and the second stress does not exceed 60 Mpa.

公开(公告)号：US10950588B2

公开(公告)日：2021-03-16

申请号：US16027374

申请日：2018-07-05

Applicant: Industrial Technology Research Institute

Inventor： Cheng-Hung Yu ,  Tai-Jui Wang ,  Chieh-Wei Feng ,  Wei-Yuan Cheng

IPC: H01L25/16 ,  H01L23/31 ,  H01L23/538 ,  H01L23/60 ,  H01L23/00 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L29/786

Abstract: A chip package structure including a redistribution structure layer, at least one chip, and an encapsulant is provided. The redistribution structure layer includes at least one redistribution circuit, at least one transistor electrically connected to the redistribution circuit, and a plurality of conductive vias electrically connected to the redistribution circuit and the transistor. The chip is disposed on the redistribution structure layer and electrically connected to the redistribution structure layer. The encapsulant is disposed on the redistribution structure layer and at least encapsulates the chip. A manufacturing method of a chip package structure is also provided.

公开(公告)号：US20190013378A1

公开(公告)日：2019-01-10

申请号：US15691755

申请日：2017-08-31

Applicant: Industrial Technology Research Institute ,  Intellectual Property Innovation Corporation

Inventor： Tai-Jui Wang ,  Chieh-Wei Feng ,  Meng-Jung Yang ,  Wei-Han Chen ,  Shao-An Yan ,  Tsu-Chiang Chang

IPC: H01L27/32

CPC classification number: H01L27/3276 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1262 ,  H01L27/3262 ,  H01L27/3265 ,  H01L27/3272 ,  H01L2227/323

Abstract: A pixel structure including a substrate, a power wire, a planarization layer, a drive circuit and a conductive structure is provided. The substrate has a layout area and a light-transmitting area located outside the layout area. The power wire is disposed on the layout area of the substrate. The power wire includes a shielding layer. The planarization layer is disposed on the substrate and covers the power wire. The drive circuit is disposed on the planarization layer and corresponds to the layout area. The drive circuit includes a first active device. The shielding layer overlaps with the first active device. The conductive structure is disposed in the planarization layer and distributed corresponding to the layout area. The power wire is electrically connected with the drive circuit through the conductive structure. A display panel is also provided.

公开(公告)号：US20250126722A1

公开(公告)日：2025-04-17

申请号：US18916714

申请日：2024-10-16

Applicant: Industrial Technology Research Institute

Inventor： Chieh-Wei Feng ,  Cheng-Yueh Chang ,  Tai-Jui Wang

IPC: H05K3/40 ,  H05K1/11 ,  H05K1/18

Abstract: A circuit compensation method applied to pattern displacement includes: disposing at least one chip on a carrier; measuring a shift of the chip, performing circuit position compensation on a predetermined pattern of a redistribution layer, and calculating a resistance difference of the pattern before and after the circuit position compensation; estimating a circuit proportion and a range of resistance variation in the pattern needed for resistance compensation after the circuit position compensation according to the resistance difference; determining a compensation position and a scheme of circuit proportion and adjusting a circuit width, area, length, pattern, or combination thereof of a circuit within the circuit proportion according to the resistance difference; outputting a picture file of the pattern after the circuit position and resistance compensation; and forming the redistribution layer according to the picture file and electrically connecting the redistribution layer to the chip. A circuit structure is also provided.

公开(公告)号：US20240130657A1

公开(公告)日：2024-04-25

申请号：US18454074

申请日：2023-08-23

Applicant: Industrial Technology Research Institute

Inventor： Hsien-Wei Chiu ,  Tai-Jui Wang ,  Chieh-Wei Feng ,  Jui-Wen Yang

IPC: A61B5/27 ,  A61B5/00

CPC classification number: A61B5/27 ,  A61B5/6804

Abstract: A physiological sensing device for sensing physiological signal of an organism is provided. The physiological sensing device includes a sensing chip, a coupling sensing electrode and a coupling dielectric stacked layer. The coupling sensing electrode is electrically connected to the sensing chip. The coupling dielectric stacked layer covers the coupling sensing electrode. The coupling dielectric stacked layer is located between the coupling sensing electrode and the organism. The coupling dielectric stacked layer includes a first dielectric layer and a second dielectric layer. The dielectric constant of the second dielectric layer is greater than that of the first dielectric layer. The second dielectric layer is located between the first dielectric layer and the organism.

公开(公告)号：US11839120B2

公开(公告)日：2023-12-05

申请号：US17037737

申请日：2020-09-30

Applicant: Industrial Technology Research Institute

Inventor： Wei-Chung Chen ,  Wen-Yu Kuo ,  Chieh-Wei Feng ,  Tai-Jui Wang

IPC: H10K59/131 ,  H10K59/121 ,  H10K59/122

CPC classification number: H10K59/131 ,  H10K59/121 ,  H10K59/122

Abstract: An electronic device including a pixel array structure, a redistribution structure, and a plurality of conductive via structures is provided. The pixel array structure includes a plurality of signal lines. The redistribution structure overlaps the pixel array structure and includes a plurality of conductive lines. The conductive via structures electrically connect the signal lines of the pixel array structure and the conductive lines of the redistribution structure. At least one of the conductive via structures shares at least one conductive layer with the pixel array structure.

公开(公告)号：US11387230B2

公开(公告)日：2022-07-12

申请号：US16183735

申请日：2018-11-08

Applicant: Industrial Technology Research Institute

Inventor： Cheng-Hung Yu ,  Tai-Jui Wang ,  Chieh-Wei Feng ,  Yu-Hua Chung

IPC: H01L27/02 ,  H02H9/04 ,  H01L23/538 ,  H01L27/12

Abstract: A system in package structure and an electrostatic discharge protection structure thereof are provided. The electrostatic discharge protection structure includes a redistribution layer and a first transistor array. The redistribution layer has a first electrode and a second electrode. The first transistor array is coupled to a pin end of at least one integrated circuit, the first electrode and the second electrode. The first transistor array has a plurality of transistors. A plurality of first transistors of the transistors are coupled in parallel, and a plurality of second transistors of the transistors are coupled in parallel. The first transistors and the second transistors are configured to be turned on for dissipating an electrostatic discharge current.

公开(公告)号：US20190341373A1

公开(公告)日：2019-11-07

申请号：US16027374

申请日：2018-07-05

Applicant: Industrial Technology Research Institute

Inventor： Cheng-Hung Yu ,  Tai-Jui Wang ,  Chieh-Wei Feng ,  Wei-Yuan Cheng

IPC: H01L25/16 ,  H01L23/31 ,  H01L23/538 ,  H01L23/60 ,  H01L23/00 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56

Abstract: A chip package structure including a redistribution structure layer, at least one chip, and an encapsulant is provided. The redistribution structure layer includes at least one redistribution circuit, at least one transistor electrically connected to the redistribution circuit, and a plurality of conductive vias electrically connected to the redistribution circuit and the transistor. The chip is disposed on the redistribution structure layer and electrically connected to the redistribution structure layer. The encapsulant is disposed on the redistribution structure layer and at least encapsulates the chip. A manufacturing method of a chip package structure is also provided.