公开(公告)号：US20180136010A1

公开(公告)日：2018-05-17

申请号：US15607389

申请日：2017-05-26

Applicant: Industrial Technology Research Institute

Inventor： Sih-Han Li ,  Shyh-Shyuan Sheu ,  Ya-Wen Yang ,  Chih-Ping Cheng ,  Chih-Sheng Lin

IPC: G01D3/02 ,  H03K17/30 ,  G01D18/00

CPC classification number: G01D3/022 ,  G01B2210/60 ,  G01D18/008 ,  H03K17/30

Abstract: A sensor interface circuit and sensor output adjusting method are provided. The sensor interface circuit includes a processor and a gain control circuit. The processor obtains information of a linear region of a sensor to set a configuration corresponding to the sensor. The gain control circuit is coupled to the processor, performs a return-to-zero operation for a maximum electronic value and a minimum electronic value corresponding to the linear region and performs a full-scale operation for a slope of the linear region according to the maximum input range of an analog-to-digital converter which is a subsequent-stage circuit of the sensor interface circuit.

公开(公告)号：US09368271B2

公开(公告)日：2016-06-14

申请号：US14693866

申请日：2015-04-22

Applicant: Industrial Technology Research Institute

Inventor： Sih-Han Li ,  Chih-Sheng Lin

IPC: H01F5/00 ,  H01F27/28 ,  H01F27/29

CPC classification number: H01F27/2804 ,  H01F5/00 ,  H01F27/2823 ,  H01F27/29 ,  H01F2027/2809

Abstract: First and second paths of the primary-coil of the transformer are located at different sides of the symmetry-line. First terminals of the first and second paths are first and second ports of the primary-coil. Second terminals of the first and second paths are connected to each other. Two partial paths of the first path are connected to each other by TSV. Two partial paths of the second path are connected to each other by TSV. Third and fourth paths of the secondary-coil of the transformer are located on different sides of the symmetry-line. First terminals of the third and fourth paths are first and second ports of the secondary-coil. Second terminals of the third and fourth paths are connected to each other. Two partial paths of the third path are connected to each other by TSV. Two partial paths of the fourth path are connected to each other by TSV.

Abstract translation: 变压器的初级线圈的第一和第二路径位于对称线的不同侧。 第一和第二路径的第一端子是初级线圈的第一和第二端口。 第一和第二路径的第二端子彼此连接。 第一路径的两个部分路径通过TSV相互连接。 第二路径的两个部分路径通过TSV相互连接。 变压器的次级线圈的第三和第四路径位于对称线的不同侧。 第三和第四路径的第一端子是次级线圈的第一和第二端口。 第三和第四路径的第二端子彼此连接。 第三路径的两个部分路径通过TSV相互连接。 第四路径的两个部分路径通过TSV相互连接。

公开(公告)号：US20160012958A1

公开(公告)日：2016-01-14

申请号：US14693866

申请日：2015-04-22

Applicant: Industrial Technology Research Institute

Inventor： Sih-Han Li ,  Chih-Sheng Lin

IPC: H01F27/28 ,  H01F27/29

CPC classification number: H01F27/2804 ,  H01F5/00 ,  H01F27/2823 ,  H01F27/29 ,  H01F2027/2809

Abstract: First and second paths of the primary-coil of the transformer are located at different sides of the symmetry-line. First terminals of the first and second paths are first and second ports of the primary-coil. Second terminals of the first and second paths are connected to each other. Two partial paths of the first path are connected to each other by TSV. Two partial paths of the second path are connected to each other by TSV. Third and fourth paths of the secondary-coil of the transformer are located on different sides of the symmetry-line. First terminals of the third and fourth paths are first and second ports of the secondary-coil. Second terminals of the third and fourth paths are connected to each other. Two partial paths of the third path are connected to each other by TSV. Two partial paths of the fourth path are connected to each other by TSV.

Abstract translation: 变压器的初级线圈的第一和第二路径位于对称线的不同侧。 第一和第二路径的第一端子是初级线圈的第一和第二端口。 第一和第二路径的第二端子彼此连接。 第一路径的两个部分路径通过TSV相互连接。 第二路径的两个部分路径通过TSV相互连接。 变压器的次级线圈的第三和第四路径位于对称线的不同侧。 第三和第四路径的第一端子是次级线圈的第一和第二端口。 第三和第四路径的第二端子彼此连接。 第三路径的两个部分路径通过TSV相互连接。 第四路径的两个部分路径通过TSV相互连接。

公开(公告)号：US11741189B2

公开(公告)日：2023-08-29

申请号：US18155762

申请日：2023-01-18

Applicant: Industrial Technology Research Institute

Inventor： Chih-Sheng Lin ,  Jian-Wei Su ,  Tuo-Hung Hou ,  Sih-Han Li ,  Fu-Cheng Tsai ,  Yu-Hui Lin

IPC: G11C11/412 ,  G06F17/16

CPC classification number: G06F17/16 ,  G11C11/412

Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element. A first terminal of the first semiconductor element receives a bias voltage. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit. A second terminal of the third semiconductor element is adapted to receive a reference voltage. A control terminal of the third semiconductor element receives an inverted signal of the computing word-line. A first terminal of the fourth semiconductor element is coupled to a first computing bit-line. A second terminal of the fourth semiconductor element is coupled to a second computing bit-line.

公开(公告)号：US20210397675A1

公开(公告)日：2021-12-23

申请号：US17013646

申请日：2020-09-06

Applicant: Industrial Technology Research Institute

Inventor： Chih-Sheng Lin ,  Jian-Wei Su ,  Tuo-Hung Hou ,  Sih-Han Li ,  Fu-Cheng Tsai ,  Yu-Hui Lin

IPC: G06F17/16 ,  G11C11/412

Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, and a third semiconductor element. A first terminal of the first semiconductor element is coupled to a first computing bit-line. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to the memory cell circuit. A first terminal of the second semiconductor element is coupled to a second terminal of the first semiconductor element. A first terminal of the third semiconductor element is coupled to a second terminal of the second semiconductor element. A second terminal of the third semiconductor element is coupled to a second computing bit-line. A control terminal of the third semiconductor element receives a bias voltage.

公开(公告)号：US10324054B2

公开(公告)日：2019-06-18

申请号：US16178599

申请日：2018-11-02

Applicant: Industrial Technology Research Institute

Inventor： Sih-Han Li ,  Chih-Sheng Lin ,  Kuan-Wei Chen ,  Erh-Hao Chen ,  Shyh-Shyuan Sheu

IPC: G01N27/12

Abstract: A method of manufacturing a sensor device is provided. In the method, sensing electrodes are formed on a substrate, a sensing material layer is formed on the sensing electrodes. The sensing material layer is etched to form a first nanowire sensing region, a second nanowire sensing region and a third nanowire sensing region respectively between every two sensing electrodes of the sensing electrodes. A dielectric layer is formed to cover the first nanowire sensing region, the second nanowire sensing region and the third nanowire sensing region, and the first nanowire sensing region and the third nanowire sensing region are exposed.

公开(公告)号：US20190154473A1

公开(公告)日：2019-05-23

申请号：US15851609

申请日：2017-12-21

Applicant: Industrial Technology Research Institute

Inventor： Sih-Han Li ,  Chih-Sheng Lin ,  Ya-Wen Yang ,  Kuan-Wei Chen ,  Shyh-Shyuan Sheu

IPC: G01D18/00

Abstract: A readout circuit for a sensor and a readout method thereof are provided. The readout circuit includes a reference circuit, a compensated circuit, and a signal processing circuit. The reference circuit provides a direct current (DC) signal. The compensated circuit is coupled to the reference circuit. The compensated circuit obtains an analog sensing signal of the sensor, obtains the DC signal from the reference circuit, and provides a compensated signal according to the analog sensing signal and the DC signal. The signal processing circuit is coupled to the compensated circuit. The signal processing circuit processes the compensated signal to convert the compensated signal into a digital sensing signal. The compensated circuit subtracts the DC signal from the analog sensing signal to provide the compensated signal.

公开(公告)号：US10101175B2

公开(公告)日：2018-10-16

申请号：US15607389

申请日：2017-05-26

Applicant: Industrial Technology Research Institute

Inventor： Sih-Han Li ,  Shyh-Shyuan Sheu ,  Ya-Wen Yang ,  Chih-Ping Cheng ,  Chih-Sheng Lin

IPC: G01D3/02 ,  G01D18/00 ,  H03K17/30

Abstract: A sensor interface circuit and sensor output adjusting method are provided. The sensor interface circuit includes a processor and a gain control circuit. The processor obtains information of a linear region of a sensor to set a configuration corresponding to the sensor. The gain control circuit is coupled to the processor, performs a return-to-zero operation for a maximum electronic value and a minimum electronic value corresponding to the linear region and performs a full-scale operation for a slope of the linear region according to the maximum input range of an analog-to-digital converter which is a subsequent-stage circuit of the sensor interface circuit.

公开(公告)号：US20170122892A1

公开(公告)日：2017-05-04

申请号：US14961906

申请日：2015-12-08

Applicant: Industrial Technology Research Institute

Inventor： Sih-Han Li ,  Chih-Sheng Lin ,  Kuan-Wei Chen ,  Erh-Hao Chen ,  Shyh-Shyuan Sheu

IPC: G01N27/12

CPC classification number: G01N27/121 ,  G01N27/127

Abstract: A sensor device and a method of manufacturing the same are provided. The sensor device includes a substrate, a plurality of sensing electrodes, a humidity nanowire sensor, a temperature nanowire sensor, and a gas nanowire sensor. The sensing electrodes are formed on the substrate, and the humidity, the temperature and the gas nanowire sensors are also on the substrate. The humidity nanowire sensor includes an exposed first nanowire sensing region, the temperature nanowire sensor includes a second nanowire sensing region, and the gas nanowire sensor includes a third nanowire sensing region.

公开(公告)号：US11599600B2

公开(公告)日：2023-03-07

申请号：US17013646

申请日：2020-09-06

Applicant: Industrial Technology Research Institute

Inventor： Chih-Sheng Lin ,  Jian-Wei Su ,  Tuo-Hung Hou ,  Sih-Han Li ,  Fu-Cheng Tsai ,  Yu-Hui Lin

IPC: G11C11/412 ,  G06F17/16

Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, and a third semiconductor element. A first terminal of the first semiconductor element is coupled to a first computing bit-line. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to the memory cell circuit. A first terminal of the second semiconductor element is coupled to a second terminal of the first semiconductor element. A first terminal of the third semiconductor element is coupled to a second terminal of the second semiconductor element. A second terminal of the third semiconductor element is coupled to a second computing bit-line. A control terminal of the third semiconductor element receives a bias voltage.