公开(公告)号：US20160077905A1

公开(公告)日：2016-03-17

申请号：US14484427

申请日：2014-09-12

Applicant: INTEL CORPORATION

Inventor： Sankaran Menon ,  Babu Trp ,  Rolf Kuehnis

IPC: G06F11/07

CPC classification number: G06F11/3648

Abstract: In an embodiment, a debug architecture for a processor/System on Chip (SoC) etc., includes a central debug unit to receive one or more functional debug signals, the central debug unit further configured to receive debug information from at least one firmware source, at least one software source, and at least one hardware source, and to output compressed debug information; a system trace module to receive the compressed debug information and to time stamp the compressed debug information; a parallel trace interface to receive the time stamped compressed debug information and to parallelize the time stamped compressed debug information; and an output unit to output the parallelized time stamped compressed debug information on one of a plurality of output paths. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，用于处理器/片上系统（SoC）等的调试架构包括用于接收一个或多个功能调试信号的中央调试单元，所述中央调试单元还被配置为从至少一个固件源接收调试信息 ，至少一个软件源和至少一个硬件源，并输出压缩调试信息; 系统跟踪模块，用于接收压缩的调试信息并对压缩的调试信息进行时间戳; 并行跟踪接口，用于接收时间戳的压缩调试信息，并且并行化时间戳的压缩调试信息; 以及输出单元，用于在多个输出路径之一上输出并行化的时间戳压缩调试信息。 描述和要求保护其他实施例。

公开(公告)号：US09753836B2

公开(公告)日：2017-09-05

申请号：US14484427

申请日：2014-09-12

Applicant: Intel Corporation

Inventor： Sankaran Menon ,  Babu Trp ,  Rolf Kuehnis

IPC: G06F11/00 ,  G06F11/36

CPC classification number: G06F11/3648

Abstract: In an embodiment, a debug architecture for a processor/System on Chip (SoC) etc., includes a central debug unit to receive one or more functional debug signals, the central debug unit further configured to receive debug information from at least one firmware source, at least one software source, and at least one hardware source, and to output compressed debug information; a system trace module to receive the compressed debug information and to time stamp the compressed debug information; a parallel trace interface to receive the time stamped compressed debug information and to parallelize the time stamped compressed debug information; and an output unit to output the parallelized time stamped compressed debug information on one of a plurality of output paths. Other embodiments are described and claimed.