公开(公告)号：US20200006329A1

公开(公告)日：2020-01-02

申请号：US16024058

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： AARON D. LILAK ,  GILBERT DEWEY ,  CHENG-YING HUANG ,  CHRISTOPHER JEZEWSKI ,  EHREN MANNEBACH ,  RISHABH MEHANDRU ,  PATRICK MORROW ,  ANAND S. MURTHY ,  ANH PHAN ,  WILLY RACHMADY

IPC: H01L27/088 ,  H01L23/522 ,  H01L23/48 ,  H01L21/768 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/092 ,  H01L23/00

Abstract: Stacked transistor structures having a conductive interconnect between source/drain regions of upper and lower transistors. In some embodiments, the interconnect is provided, at least in part, by highly doped epitaxial material deposited in the upper transistor's source/drain region. In such cases, the epitaxial material seeds off of an exposed portion of semiconductor material of or adjacent to the upper transistor's channel region and extends downward into a recess that exposes the lower transistor's source/drain contact structure. The epitaxial source/drain material directly contacts the lower transistor's source/drain contact structure, to provide the interconnect. In other embodiments, the epitaxial material still seeds off the exposed semiconductor material of or proximate to the channel region and extends downward into the recess, but need not contact the lower contact structure. Rather, a metal-containing contact structure passes through the epitaxial material of the upper source/drain region and contacts the lower transistor's source/drain contact structure.