公开(公告)号：US20190341297A1

公开(公告)日：2019-11-07

申请号：US16473902

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： AARON D. LILAK ,  RISHABH MEHANDRU ,  PATRICK MORROW

IPC: H01L21/762 ,  H01L27/12 ,  H01L21/8234

Abstract: Techniques are disclosed for forming integrated circuit structures having a plurality of non-planar transistors. An insulation structure is provided between channel, source, and drain regions of neighboring fins. The insulation structure is formed during back side processing, wherein at least a first portion of the isolation material between adjacent fins is recessed to expose a sub-channel portion of the semiconductor fins. A spacer material is then deposited at least on the exposed opposing sidewalls of the exposed sub-channel portion of each fin. The isolation material is then further recessed to form an air gap between gate, source, and drain regions of neighboring fins. The air gap electrically isolates the source/drain regions of one fin from the source/drain regions of an adjacent fin, and likewise isolates the gate region of the one fin from the gate region of the adjacent fin. The air gap can be filled with a dielectric material.

公开(公告)号：US20200294998A1

公开(公告)日：2020-09-17

申请号：US16355195

申请日：2019-03-15

Applicant: INTEL CORPORATION

Inventor： AARON D. LILAK ,  EHREN MANNEBACH ,  ANH PHAN ,  RICHARD E. SCHENKER ,  STEPHANIE A. BOJARSKI ,  WILLY RACHMADY ,  PATRICK R. MORROW ,  JEFFERY D. BIELEFELD ,  GILBERT DEWEY ,  HUI JAE YOO

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/532

Abstract: Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.

公开(公告)号：US20180331183A1

公开(公告)日：2018-11-15

申请号：US15775786

申请日：2015-12-17

Applicant: Intel Corporation

Inventor： AARON D. LILAK ,  RISHABH MEHANDRU ,  HAROLD W. KENNEL ,  PAUL B. FISCHER ,  STEPHEN M. CEA

IPC: H01L29/10 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L23/00

CPC classification number: H01L29/1083 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L23/48 ,  H01L24/16 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/78 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/13067 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2224/13099

Abstract: Embodiments of the present disclosure describe techniques for backside isolation for devices of an integrated circuit (IC) and associated configurations. The IC may include a plurality of devices (e.g., transistors) formed on a semiconductor substrate. The semiconductor substrate may include substrate regions on which one or more devices are formed. Trenches may be disposed between the devices on the semiconductor substrate. Portions of the semiconductor substrate between the substrate regions may be removed to expose the corresponding trenches and form isolation regions. An insulating material may be formed in the isolation regions. Other embodiments may be described and/or claimed.

公开(公告)号：US20200006331A1

公开(公告)日：2020-01-02

申请号：US16024080

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： AARON D. LILAK ,  GILBERT DEWEY ,  WILLY RACHMADY ,  RAMI HOURANI ,  STEPHANIE A. BOJARSKI ,  RISHABH MEHANDRU ,  ANH PHAN ,  EHREN MANNEBACH

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06

Abstract: A stacked transistor architecture has a fin structure that includes lower and upper portions separated by an isolation region built into the fin structure. Upper and lower gate structures on respective upper and lower fin structure portions may be different from one another (e.g., with respect to work function metal and/or gate dielectric thickness). One example methodology includes depositing lower gate structure materials on the lower and upper channel regions, recessing those materials to re-expose the upper channel region, and then re-depositing upper gate structure materials on the upper channel region. Another example methodology includes depositing a sacrificial protective layer on the upper channel region. The lower gate structure materials are then deposited on both the exposed lower channel region and sacrificial protective layer. The lower gate structure materials and sacrificial protective layer are then recessed to re-expose upper channel region so that upper gate structure materials can be deposited.

公开(公告)号：US20200006330A1

公开(公告)日：2020-01-02

申请号：US16024076

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： AARON D. LILAK ,  ANH PHAN ,  EHREN MANNEBACH ,  CHENG-YING HUANG ,  STEPHANIE A. BOJARSKI ,  GILBERT DEWEY ,  ORB ACTON ,  WILLY RACHMADY

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/08 ,  H01L29/06 ,  H01L23/528 ,  H01L29/78 ,  H01L21/762

Abstract: Stacked transistor structures having a conductive interconnect between upper and lower transistors. In an embodiment, the interconnect is formed by first provisioning a protective layer over an area to be protected (gate dielectric or other sensitive material) of upper transistor, and then etching material adjacent and below the protected area to expose an underlying contact point of lower transistor. A metal is deposited into the void created by the etch to provide the interconnect. The protective layer is resistant to the etch process and is preserved in the structure, and in some cases may be utilized as a work-function metal. In an embodiment, the protective layer is formed by deposition of reactive semiconductor and metal material layers which are subsequently transformed into a work function metal or work function metal-containing compound. A remnant of unreacted reactive semiconductor material may be left in structure and collinear with protective layer.

公开(公告)号：US20200006340A1

公开(公告)日：2020-01-02

申请号：US16024064

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： AARON D. LILAK ,  RISHABH MEHANDRU ,  ANH PHAN ,  GILBERT DEWEY ,  WILLY RACHMADY ,  STEPHEN M. CEA ,  SAYED HASAN ,  KERRYANN M. FOLEY ,  PATRICK MORROW ,  COLIN D. LANDON ,  EHREN MANNEBACH

IPC: H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L29/775 ,  H01L29/423

Abstract: Stacked transistor structures and methods of forming same. In an embodiment, a stacked transistor structure has a wide central pedestal region and at least one relatively narrower channel region above and/or below the wider central pedestal region. The upper and lower channel regions are configured with a non-planar architecture, and include one or more semiconductor fins, nanowires, and/or nanoribbons. The top and bottom channel regions may be configured the same or differently, with respect to shape and/or semiconductor materials. In some cases, an outermost sidewall of one or both the top and/or bottom channel region structures, is collinear with an outermost sidewall of the wider central pedestal region. In some such cases, the outermost sidewall of the top channel region structure is collinear with the outermost sidewall of the bottom channel region structure. Top and bottom transistor structures (NMOS/PMOS) may be formed using the top and bottom channel region structures.

公开(公告)号：US20200006329A1

公开(公告)日：2020-01-02

申请号：US16024058

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： AARON D. LILAK ,  GILBERT DEWEY ,  CHENG-YING HUANG ,  CHRISTOPHER JEZEWSKI ,  EHREN MANNEBACH ,  RISHABH MEHANDRU ,  PATRICK MORROW ,  ANAND S. MURTHY ,  ANH PHAN ,  WILLY RACHMADY

IPC: H01L27/088 ,  H01L23/522 ,  H01L23/48 ,  H01L21/768 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/092 ,  H01L23/00

Abstract: Stacked transistor structures having a conductive interconnect between source/drain regions of upper and lower transistors. In some embodiments, the interconnect is provided, at least in part, by highly doped epitaxial material deposited in the upper transistor's source/drain region. In such cases, the epitaxial material seeds off of an exposed portion of semiconductor material of or adjacent to the upper transistor's channel region and extends downward into a recess that exposes the lower transistor's source/drain contact structure. The epitaxial source/drain material directly contacts the lower transistor's source/drain contact structure, to provide the interconnect. In other embodiments, the epitaxial material still seeds off the exposed semiconductor material of or proximate to the channel region and extends downward into the recess, but need not contact the lower contact structure. Rather, a metal-containing contact structure passes through the epitaxial material of the upper source/drain region and contacts the lower transistor's source/drain contact structure.