公开(公告)号：US20200185526A1

公开(公告)日：2020-06-11

申请号：US16785975

申请日：2020-02-10

Applicant: Intel Corporation

Inventor： Seiyon KIM ,  Rafael RIOS ,  Fahmida FERDOUSI ,  Kelin J. KUHN

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L21/306 ,  H01L21/02 ,  H01L29/423 ,  H01L29/16 ,  H01L29/775 ,  B82Y40/00 ,  B82Y10/00

Abstract: Non-planar semiconductor devices having hybrid geometry-based active regions are described. For example, a semiconductor device includes a hybrid channel region including a nanowire portion disposed above an omega-FET portion disposed above a fin-FET portion. A gate stack is disposed on exposed surfaces of the hybrid channel region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the hybrid channel region.

公开(公告)号：US20160276484A1

公开(公告)日：2016-09-22

申请号：US15024714

申请日：2013-12-19

Applicant: INTEL CORPORATION

Inventor： Seiyon KIM ,  Rafael RIOS ,  Fahmida FERDOUSI ,  Kelin J. KUHN

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/10 ,  H01L21/306 ,  H01L21/02 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66

Abstract: Non-planar semiconductor devices having hybrid geometry-based active regions are described. For example, a semiconductor device includes a hybrid channel region including a nanowire portion disposed above an omega-FET portion disposed above a fin-FET portion. A gate stack is disposed on exposed surfaces of the hybrid channel region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the hybrid channel region.

Abstract translation: 描述了具有基于混合几何的有源区域的非平面半导体器件。 例如，半导体器件包括混合沟道区域，其包括设置在鳍状FET部分上方的Ω-FET部分上方的纳米线部分。 栅极叠层设置在混合沟道区域的暴露表面上。 栅极堆叠包括栅极电介质层和设置在栅极介电层上的栅电极。 源极和漏极区域设置在混合沟道区域的两侧。

公开(公告)号：US20180358467A1

公开(公告)日：2018-12-13

申请号：US16108610

申请日：2018-08-22

Applicant: Intel Corporation

Inventor： Seiyon KIM ,  Rafael RIOS ,  Fahmida FERDOUSI ,  Kelin J. KUHN

IPC: H01L29/78 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/775 ,  H01L29/66 ,  H01L29/423 ,  H01L29/16 ,  H01L29/10 ,  H01L29/06 ,  H01L21/306 ,  H01L21/02 ,  B82Y40/00

Abstract: Non-planar semiconductor devices having hybrid geometry-based active regions are described. For example, a semiconductor device includes a hybrid channel region including a nanowire portion disposed above an omega-FET portion disposed above a fin-FET portion. A gate stack is disposed on exposed surfaces of the hybrid channel region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the hybrid channel region.