公开(公告)号：US20180122901A1

公开(公告)日：2018-05-03

申请号：US15859226

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Seiyon KIM ,  Kelin J. KUHN ,  Tahir GHANI ,  Anand S. MURTHY ,  Mark ARMSTRONG ,  Rafael RIOS ,  Abhijit Jayant PETHE ,  Willy RACHMADY

IPC: H01L29/06 ,  H01L29/66

CPC classification number: H01L29/0673 ,  B82Y40/00 ,  H01L21/30604 ,  H01L21/3105 ,  H01L21/31155 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78 ,  H01L29/78696

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

公开(公告)号：US20170133462A1

公开(公告)日：2017-05-11

申请号：US15410649

申请日：2017-01-19

Applicant: Intel Corporation

Inventor： Kelin J. KUHN ,  Seiyon KIM ,  Rafael RIOS ,  Stephen M. CEA ,  Martin D. GILES ,  Annalisa CAPPELLANI ,  Titash RAKSHIT ,  Peter CHANG ,  Willy RACHMADY

IPC: H01L29/06 ,  H01L21/762 ,  H01L27/092 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165 ,  H01L29/417 ,  H01L29/423 ,  B82Y10/00 ,  H01L27/12

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/76224 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/165 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

公开(公告)号：US20220115505A1

公开(公告)日：2022-04-14

申请号：US17558425

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Kelin J. KUHN ,  Kaizad MISTRY ,  Mark BOHR ,  Chris AUTH

IPC: H01L29/417 ,  H01L21/768 ,  H01L23/485 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: Methods of fabricating a first contact to a semiconductor device, which fundamentally comprises providing a semiconductor device formed on a substrate. The substrate further includes a conductive surface. A dielectric layer is formed over the substrate and has an opening exposing the conductive surface. The opening extends an entire length of the semiconductor device, partway down the entire length of the device, extending from the device onto adjacent field of the device, or and a combination thereof. A barrier layer is formed within the opening. A copper containing material fills the opening to form a first contact to the semiconductor device.

公开(公告)号：US20200185526A1

公开(公告)日：2020-06-11

申请号：US16785975

申请日：2020-02-10

Applicant: Intel Corporation

Inventor： Seiyon KIM ,  Rafael RIOS ,  Fahmida FERDOUSI ,  Kelin J. KUHN

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L21/306 ,  H01L21/02 ,  H01L29/423 ,  H01L29/16 ,  H01L29/775 ,  B82Y40/00 ,  B82Y10/00

Abstract: Non-planar semiconductor devices having hybrid geometry-based active regions are described. For example, a semiconductor device includes a hybrid channel region including a nanowire portion disposed above an omega-FET portion disposed above a fin-FET portion. A gate stack is disposed on exposed surfaces of the hybrid channel region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the hybrid channel region.

公开(公告)号：US20200152738A1

公开(公告)日：2020-05-14

申请号：US16740132

申请日：2020-01-10

Applicant: Intel Corporation

Inventor： Seiyon KIM ,  Kelin J. KUHN ,  Tahir GHANI ,  Anand S. MURTHY ,  Mark ARMSTRONG ,  Rafael RIOS ,  Abhijit Jayant PETHE ,  Willy RACHMADY

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L21/3115 ,  H01L21/3105 ,  H01L21/306 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

公开(公告)号：US20190051725A1

公开(公告)日：2019-02-14

申请号：US16153456

申请日：2018-10-05

Applicant: Intel Corporation

Inventor： Seiyon KIM ,  Kelin J. KUHN ,  Tahir GHANI ,  Anand S. MURTHY ,  Mark ARMSTRONG ,  Rafael RIOS ,  Abhijit Jayant PETHE ,  Willy RACHMADY

IPC: H01L29/06 ,  H01L29/423

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

公开(公告)号：US20170358658A1

公开(公告)日：2017-12-14

申请号：US15506205

申请日：2014-09-26

Applicant: INTEL CORPORATION

Inventor： Rafael RIOS ,  Kelin J. KUHN ,  Seiyon KIM ,  Justin R. Weber

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/66439 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/122 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24 ,  H01L29/42356 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/775 ,  H01L29/778 ,  H01L29/78636 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696 ,  H01L49/00

Abstract: Embodiments of the invention include metal oxide metal field effect transistors (MOMFETs) and methods of making such devices. In embodiments, the MOMFET device includes a source and a drain with a channel disposed between the source and the drain. According to an embodiment, the channel has at least one confined dimension that produces a quantum confinement effect in the channel. In an embodiment, the MOMFET device also includes a gate electrode that is separated from the channel by a gate dielectric. According to embodiments, the band-gap energy of the channel may be modulated by changing the size of the channel, the material used for the channel, and/or the surface termination applied to the channel. Embodiments also include forming an type device and a P-type device by controlling the work-function of the source and drain relative to the conduction band and valance band energies of the channel.

公开(公告)号：US20170162676A1

公开(公告)日：2017-06-08

申请号：US15434981

申请日：2017-02-16

Applicant: Intel Corporation

Inventor： Annalisa CAPPELLANI ,  Stephen M. CEA ,  Tahir GHANI ,  Harry GOMEZ ,  Jack T. KAVALIEROS ,  Patrick H. KEYS ,  Seiyon KIM ,  Kelin J. KUHN ,  Aaron D. LILAK ,  Rafael RIOS ,  Mayank SAHNI

IPC: H01L29/66 ,  H01L21/762 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/66818 ,  B82Y10/00 ,  H01L21/762 ,  H01L21/76216 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a semiconductor substrate. The semiconductor body includes a channel region and a pair of source and drain regions on either side of the channel region. An isolation pedestal is disposed between the semiconductor body and the semiconductor substrate. A gate electrode stack at least partially surrounds a portion of the channel region of the semiconductor body.

公开(公告)号：US20170158501A1

公开(公告)日：2017-06-08

申请号：US15301337

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： Jorge A. MUNOZ ,  Dmitri E. NIKONOV ,  Kelin J. KUHN ,  Patrick THEOFANIS ,  Chytra PAWASHE ,  Kevin LIN ,  Seiyon KIM

IPC: B82B1/00 ,  H01H59/00 ,  B82B3/00 ,  H01L29/66 ,  H01L29/84 ,  H01L29/82

CPC classification number: B82B1/005 ,  B81B3/0016 ,  B81B7/02 ,  B81B2201/014 ,  B81B2203/0118 ,  B82B1/002 ,  B82B3/0023 ,  B82Y15/00 ,  B82Y25/00 ,  B82Y40/00 ,  H01H1/0094 ,  H01H1/54 ,  H01H59/0009 ,  H01L29/66227 ,  H01L29/82 ,  H01L29/84 ,  Y10S977/732 ,  Y10S977/838 ,  Y10S977/888 ,  Y10S977/938

Abstract: Nanoelectromechanical (NEMS) devices having nanomagnets for an improved range of operating voltages and improved control of dimensions of a cantilever are described. For example, in an embodiment, a nanoelectromechanical (NEMS) device includes a substrate layer, a first magnetic layer disposed above the substrate layer, a first dielectric layer disposed above the first magnetic layer, a second dielectric disposed above the first dielectric layer, and a cantilever disposed above the second dielectric layer. The cantilever bends from a first position to a second position towards the substrate layer when a voltage is applied to the cantilever.

公开(公告)号：US20180358467A1

公开(公告)日：2018-12-13

申请号：US16108610

申请日：2018-08-22

Applicant: Intel Corporation

Inventor： Seiyon KIM ,  Rafael RIOS ,  Fahmida FERDOUSI ,  Kelin J. KUHN

IPC: H01L29/78 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/775 ,  H01L29/66 ,  H01L29/423 ,  H01L29/16 ,  H01L29/10 ,  H01L29/06 ,  H01L21/306 ,  H01L21/02 ,  B82Y40/00

Abstract: Non-planar semiconductor devices having hybrid geometry-based active regions are described. For example, a semiconductor device includes a hybrid channel region including a nanowire portion disposed above an omega-FET portion disposed above a fin-FET portion. A gate stack is disposed on exposed surfaces of the hybrid channel region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the hybrid channel region.