公开(公告)号：US20170300332A1

公开(公告)日：2017-10-19

申请号：US15476356

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： ELMOUSTAPHA OULD-AHMED-VALL ,  ROBERT VALENTINE ,  JESUS CORBAL SAN ADRIAN ,  BRET L. TOLL ,  MARK J. CHARNEY ,  ZEEV SPERBER ,  AMIT GRADSTEIN

IPC: G06F9/30

CPC classification number: G06F9/30181 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/3802 ,  G06F12/0615

Abstract: An apparatus is described having instruction execution logic circuitry to execute first, second, third and fourth instruction. Both the first instruction and the second instruction insert a first group of input vector elements to one of multiple first non overlapping sections of respective first and second resultant vectors. The first group has a first bit width. Each of the multiple first non overlapping sections have a same bit width as the first group. Both the third instruction and the fourth instruction insert a second group of input vector elements to one of multiple second non overlapping sections of respective third and fourth resultant vectors. The second group has a second bit width that is larger than said first bit width. Each of the multiple second non overlapping sections have a same bit width as the second group. The apparatus also includes masking layer circuitry to mask the first and third instructions at a first resultant vector granularity, and, mask the second and fourth instructions at a second resultant vector granularity.

公开(公告)号：US20170329605A1

公开(公告)日：2017-11-16

申请号：US15668508

申请日：2017-08-03

Applicant: Intel Corporation

Inventor： ELMOUSTAPHA OULD-AHMED-VALL ,  ROBERT VALENTINE ,  JESUS CORBAL SAN ADRIAN ,  BRET L. TOLL ,  MARK J. CHARNEY ,  ZEEV SPERBER ,  AMIT GRADSTEIN

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30181 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/3802 ,  G06F12/0615

Abstract: An apparatus is described having instruction execution logic circuitry to execute first, second, third and fourth instruction. Both the first instruction and the second instruction insert a first group of input vector elements to one of multiple first non overlapping sections of respective first and second resultant vectors. The first group has a first bit width. Each of the multiple first non overlapping sections have a same bit width as the first group. Both the third instruction and the fourth instruction insert a second group of input vector elements to one of multiple second non overlapping sections of respective third and fourth resultant vectors. The second group has a second bit width that is larger than said first bit width. Each of the multiple second non overlapping sections have a same bit width as the second group. The apparatus also includes masking layer circuitry to mask the first and third instructions at a first resultant vector granularity, and, mask the second and fourth instructions at a second resultant vector granularity.

公开(公告)号：US20160188532A1

公开(公告)日：2016-06-30

申请号：US14583636

申请日：2014-12-27

Applicant: INTEL CORPORATION

Inventor： ELMOUSTAPHA OULD-AHMED-VALL ,  JESUS CORBAL SAN ADRIAN ,  ROBERT VALENTINE ,  MARK J. CHARNEY ,  GUILLEM SOLE ,  ROGER ESPASA

IPC: G06F15/80 ,  G06F9/30

CPC classification number: G06F15/8084 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3012 ,  G06F15/8076

Abstract: An apparatus and method for performing a vector bit shuffle. For example, one embodiment of a processor comprises: a first vector register to store a plurality of source data elements; a second vector register to store a plurality of control elements, each of the control elements comprising a plurality of bit fields, each bit field to be associated with a corresponding bit position in a destination mask register and to identify a bit from each of the source data elements to be copied to each of the particular bit positions; and vector bit shuffle logic to read each bit field from the second vector register to identify a bit from each of the source data elements and to responsively copy the bit from each of the source data elements to each of the corresponding bit positions in the destination mask register.

Abstract translation: 用于执行向量比特洗牌的装置和方法。 例如，处理器的一个实施例包括：第一向量寄存器，用于存储多个源数据元素; 用于存储多个控制元件的第二矢量寄存器，每个控制元件包括多个位域，每个位域与目的地掩模寄存器中的对应位位置相关联，并且从源中的每一个识别位 要复制到每个特定位位置的数据元素; 和向量位洗牌逻辑，以从第二向量寄存器读取每个位字段，以识别来自每个源数据元素的位，并且响应地将每个源数据元素中的位复制到目标掩码中的每个相应位位置 寄存器。

公开(公告)号：US20160188335A1

公开(公告)日：2016-06-30

申请号：US14583639

申请日：2014-12-27

Applicant: INTEL CORPORATION

Inventor： ELMOUSTAPHA OULD-AHMED-VALL ,  ROBERT VALENTINE ,  JESUS CORBAL SAN ADRIAN ,  MARK J. CHARNEY ,  GUILLEM SOLE ,  ROGER ESPASA

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30098

Abstract: An apparatus and method for performing a vector bit gather. For example, one embodiment of a processor comprises: a first vector register to store one or more source data elements; a second vector register to store one or more control elements, each of the control elements comprising a plurality of bit fields, each bit field to be associated with a corresponding bit position in a destination vector register and to identify a bit from the one or more source data elements to be copied to each of the particular bit positions; and vector bit gather logic to read each bit field from the second vector register to identify a bit from the one or more source data elements and to responsively copy the bit from each of the one or more source data elements to each of the corresponding bit positions in the destination vector register.

Abstract translation: 用于执行向量位聚合的装置和方法。 例如，处理器的一个实施例包括：第一向量寄存器，用于存储一个或多个源数据元素; 第二矢量寄存器，用于存储一个或多个控制元件，每个控制元件包括多个位域，每个位字段将与目的地向量寄存器中的相应位位置相关联，并且从一个或多个位 要复制到每个特定位位置的源数据元素; 和向量位采集逻辑，以从第二向量寄存器读取每个位域，以识别来自一个或多个源数据元素的位，并且响应地将该一个或多个源数据元素中的每个源的位复制到相应的位位置 在目的向量寄存器中。

公开(公告)号：US20200097290A1

公开(公告)日：2020-03-26

申请号：US16560223

申请日：2019-09-04

Applicant: Intel Corporation

Inventor： JESUS CORBAL SAN ADRIAN ,  ELMOUSTAPHA OULD-AHMED-VALL ,  ROBERT VALENTINE ,  MARK J. CHARNEY ,  MILIND B. GIRKAR ,  BRET L. TOLL ,  ROGER ESPASA ,  GUILLEM SOLE ,  JAIRO BALART ,  BRIAN HICKMANN

IPC: G06F9/30 ,  G06F15/80 ,  G06F16/901

Abstract: An apparatus and method for performing a vector permute. For example, one embodiment of a processor comprises: a source vector register to store a plurality of source data elements; a destination vector register to store a plurality of destination data elements; a control vector register to store a plurality of control data elements, each control data element corresponding to one of the destination data elements and including an N bit value indicating whether a source data element is to be copied to the corresponding destination data element; vector permute logic to compare the N bit value of each control data element to an N bit portion of an immediate to determine whether to copy a source data element to the corresponding destination data element, wherein if the N bit values match, then the vector permute logic is to identify a source data element using an index value included in the control data element and to responsively copy the source data element to the corresponding destination data element in the destination vector register.

公开(公告)号：US20170357510A1

公开(公告)日：2017-12-14

申请号：US15668461

申请日：2017-08-03

Applicant: Intel Corporation

Inventor： ELMOUSTAPHA OULD-AHMED-VALL ,  ROBERT VALENTINE ,  JESUS CORBAL SAN ADRIAN ,  BRET L. TOLL ,  MARK J. CHARNEY ,  ZEEV SPERBER ,  AMIT GRADSTEIN

IPC: G06F9/30

CPC classification number: G06F9/30181 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/3802 ,  G06F12/0615

Abstract: An apparatus is described having instruction execution logic circuitry to execute first, second, third and fourth instruction. Both the first instruction and the second instruction insert a first group of input vector elements to one of multiple first non overlapping sections of respective first and second resultant vectors. The first group has a first bit width. Each of the multiple first non overlapping sections have a same bit width as the first group. Both the third instruction and the fourth instruction insert a second group of input vector elements to one of multiple second non overlapping sections of respective third and fourth resultant vectors. The second group has a second bit width that is larger than said first bit width. Each of the multiple second non overlapping sections have a same bit width as the second group. The apparatus also includes masking layer circuitry to mask the first and third instructions at a first resultant vector granularity, and, mask the second and fourth instructions at a second resultant vector granularity.

公开(公告)号：US20160188530A1

公开(公告)日：2016-06-30

申请号：US14583644

申请日：2014-12-27

Applicant: INTEL CORPORATION

Inventor： JESUS CORBAL SAN ADRIAN ,  ELMOUSTAPHA OULD-AHMED-VALL ,  ROBERT VALENTINE ,  MARK J. CHARNEY ,  MILIND B. GIRKAR ,  BRET L. TOLL ,  ROGER ESPASA ,  GUILLEM SOLE ,  JAIRO BALART ,  BRIAN HICKMAN

IPC: G06F15/80 ,  G06F9/30

CPC classification number: G06F9/30036 ,  G06F7/764 ,  G06F9/30032 ,  G06F15/8053 ,  G06F15/8084 ,  G06F16/9017 ,  G06F2209/462

Abstract: An apparatus and method for performing a vector permute. For example, one embodiment of a processor comprises: a source vector register to store a plurality of source data elements; a destination vector register to store a plurality of destination data elements; a control vector register to store a plurality of control data elements, each control data element corresponding to one of the destination data elements and including an N bit value indicating whether a source data element is to be copied to the corresponding destination data element; vector permute logic to compare the N bit value of each control data element to an N bit portion of an immediate to determine whether to copy a source data element to the corresponding destination data element, wherein if the N bit values match, then the vector permute logic is to identify a source data element using an index value included in the control data element and to responsively copy the source data element to the corresponding destination data element in the destination vector register.

Abstract translation: 用于执行向量置换的装置和方法。 例如，处理器的一个实施例包括：源向量寄存器，用于存储多个源数据元素; 目的地向量寄存器，用于存储多个目的地数据元素; 用于存储多个控制数据元素的控制向量寄存器，与目的地数据元素之一对应的每个控制数据元素，并且包括指示源数据元素是否被复制到对应的目的地数据元素的N位值; 向量置换逻辑，以将每个控制数据元素的N位值与立即数的N位部分进行比较，以确定是否将源数据元素复制到对应的目标数据元素，其中如果N位值匹配，则向量置换 逻辑是使用包括在控制数据元素中的索引值来识别源数据元素，并且将源数据元素响应地复制到目的地向量寄存器中的相应目的地数据元素。