公开(公告)号：US20150309726A1

公开(公告)日：2015-10-29

申请号：US14440066

申请日：2013-11-22

Applicant: James A. MCCALL ,  Kuljit S. BAINS ,  Intel Corporation

Inventor： James A. MCCALL ,  Kuljit S. BAINS

IPC: G06F3/06 ,  G11C5/14

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0673 ,  G11C5/147 ,  G11C7/1057 ,  G11C7/1084 ,  G11C29/021 ,  G11C29/028

Abstract: Techniques and mechanisms for a memory device to concurrently receive and process signals each based on a different respective reference voltage level. In an embodiment, an input/output (I/O) interface of a memory device includes receiver circuits each to process a respective signal received via a corresponding signal line of a bus. In response to one or more configuration commands, a first receiver circuit is configured to process a first signal based on a first reference voltage level and a second receiver circuit is configured to process a second signal based on a second reference voltage level. In another embodiment, a memory controller sends the one or more configuration commands to such a memory device based on an evaluation of voltage swing characteristics each corresponding to a different respective signal line of a bus.

Abstract translation: 用于存储器件的技术和机制，用于基于不同的相应参考电压电平同时接收和处理信号。 在一个实施例中，存储器件的输入/输出（I / O）接口包括接收器电路，每个接收器电路用于处理经由总线的相应信号线接收到的相应信号。 响应于一个或多个配置命令，第一接收器电路被配置为基于第一参考电压电平处理第一信号，并且第二接收器电路被配置为基于第二参考电压电平来处理第二信号。 在另一个实施例中，存储器控制器基于对每个对应于总线的不同相应信号线的电压摆动特性的评估将一个或多个配置命令发送到这种存储器件。

公开(公告)号：US20180189214A1

公开(公告)日：2018-07-05

申请号：US15396268

申请日：2016-12-30

Applicant: INTEL CORPORATION

Inventor： James A. MCCALL ,  Zhichao ZHANG ,  Qin LI ,  Xiang LI ,  John R. DREW

IPC: G06F13/40 ,  H01R12/72

CPC classification number: G06F13/4022 ,  G06F13/4068 ,  H01R12/721

Abstract: Devices include a connecting card that may be used in a memory connector. The connecting card may include a substrate including a first substrate region and a second substrate region, a plurality of adjacent signal pathways extending from the first substrate region to the second substrate region, and a capacitor positioned between each of the adjacent signal pathways. Other embodiments are described and claimed.