-
公开(公告)号:US20250070491A1
公开(公告)日:2025-02-27
申请号:US18238381
申请日:2023-08-25
Applicant: Intel Corporation
Inventor: Saikat MONDAL , Zhichao ZHANG , Oluwafemi AKINWALE , Kemal AYGÜN
IPC: H01R12/71 , H01L23/00 , H01R13/24 , H01R13/405
Abstract: Embodiments disclosed herein include sockets and socket modules. In an embodiment, a socket module comprises a housing and a first pin through the housing in a first row of pins. In an embodiment, a second pin is through the housing in a second row of pins. In an embodiment, at least three intervening rows of pins are between the first row of pins and the second row of pins. In an embodiment, one or more pin locations in the at least three intervening rows of pins are depopulated.
-
公开(公告)号:US20200381350A1
公开(公告)日:2020-12-03
申请号:US16636620
申请日:2017-09-29
Applicant: Intel Corporation
Inventor: Sujit SHARAN , Kemal AYGUN , Zhiguo QIAN , Yidnekachew MEKONNEN , Zhichao ZHANG , Jianyong XIE
IPC: H01L23/498 , H01L23/00
Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, wherein the die comprises a plurality of high density features. An interconnect bridge is embedded in the substrate, wherein the interconnect bridge may comprise a first region disposed on a surface of the interconnect bridge comprising a first plurality of features, wherein the first plurality of features comprises a first pitch. A second region disposed on the surface of the interconnect bridge comprises a second plurality of features comprising a second pitch, wherein the second pitch is greater than the first pitch.
-
公开(公告)号:US20250014980A1
公开(公告)日:2025-01-09
申请号:US18219018
申请日:2023-07-06
Applicant: Intel Corporation
Inventor: Eric ERIKE , Anikki GIESSLER , Zhichao ZHANG , Srikant NEKKANTY , Saikat MONDAL
IPC: H01L23/498 , H01R12/52
Abstract: Embodiments disclosed herein include a liquid metal interposer. In an embodiment, the liquid metal interposer comprises a substrate with a first opening in the substrate and a second opening in the substrate. In an embodiment, a channel is between the first opening and the second opening. In an embodiment, the channel fluidically couples the first opening to the second opening.
-
公开(公告)号:US20220231394A1
公开(公告)日:2022-07-21
申请号:US17714957
申请日:2022-04-06
Applicant: Intel Corporation
Inventor: Adel A. ELSHERBINI , Mathew MANUSHAROW , Krishna BHARATH , Zhichao ZHANG , Yidnekachew S. MEKONNEN , Aleksandar ALEKSOV , Henning BRAUNISCH , Feras EID , Javier SOTO
Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.
-
公开(公告)号:US20220196935A1
公开(公告)日:2022-06-23
申请号:US17131682
申请日:2020-12-22
Applicant: Intel Corporation
Inventor: Xiaoqian LI , Nitin DESHPANDE , Omkar KARHADE , Asako TODA , Divya PRATAP , Zhichao ZHANG
IPC: G02B6/42
Abstract: Embodiments disclosed herein include photonics packages. In an embodiment, a photonics package comprises a package substrate, and a compute die over the package substrate. In an embodiment, a photonics die is also over the package substrate, and the photonics die overhangs an edge of the package substrate. In an embodiment, an integrated heat spreader (IHS) is over the compute die and the photonics die, and a fiber connector is coupled to the photonics die. In an embodiment, the fiber connector is attached to the IHS
-
公开(公告)号:US20210305138A1
公开(公告)日:2021-09-30
申请号:US16828466
申请日:2020-03-24
Applicant: Intel Corporation
Inventor: Zhichao ZHANG , Zhenguo JIANG , Haifa HARIRI , Kemal AYGÜN , Sriram SRINIVASAN
IPC: H01L23/498 , H01R12/71
Abstract: Embodiments disclosed herein include electronic packaged assemblies. In an embodiment, an electronic package comprises first and second surfaces. The second surface has a land pad in a land pad opening. The land pad is spaced away from the land pad opening by an outer gap. The land pad is a closed loop. In an embodiment, the electronic package is electrically coupled to a socket. The socket has an interconnect with a first connector and a second connector. The first connector of the interconnect is directly coupled to at least one portion of the closed loop. In an embodiment, when the first connector is coupled to at least two or more portions of the closed loop, the portions are spaced away from each other by a portion of the inner or outer gap. The closed loop comprises a conductive line continuously extending from a first end to a second end.
-
公开(公告)号:US20210210478A1
公开(公告)日:2021-07-08
申请号:US17191615
申请日:2021-03-03
Applicant: Intel Corporation
Inventor: Susheel JADHAV , Juan DOMINGUEZ , Ankur AGRAWAL , Kenneth BROWN , Yi LI , Jing CHEN , Aditi MALLIK , Xiaoyu HONG , Thomas LILJEBERG , Andrew C. ALDUINO , Ling LIAO , David HUI , Ren-Kang CHIOU , Harinadh POTLURI , Hari MAHALINGAM , Lobna KAMYAB , Sasanka KANUPARTHI , Sushrutha Reddy GUJJULA , Saeed FATHOLOLOUMI , Priyanka DOBRIYAL , Boping XIE , Abiola AWUJOOLA , Vladimir TAMARKIN , Keith MEASE , Stephen KEELE , David SCHWEITZER , Brent ROTHERMEL , Ning TANG , Suresh POTHUKUCHI , Srikant NEKKANTY , Zhichao ZHANG , Kaiyuan ZENG , Baikuan WANG , Donald TRAN , Ravindranath MAHAJAN , Baris BICEN , Grant SMITH
IPC: H01L25/18 , H01L23/473 , H01R12/71
Abstract: Embodiments disclosed herein include electronic packages for optical to electrical switching. In an embodiment, an electronic package comprises a first package substrate and a second package substrate attached to the first package substrate. In an embodiment, a die is attached to the second package substrate. In an embodiment, a plurality of photonic engines are attached to a first surface and a second surface of the first package substrate. In an embodiment, the plurality of photonic engines are communicatively coupled to the die through the first package substrate and the second package substrate.
-
公开(公告)号:US20190394876A1
公开(公告)日:2019-12-26
申请号:US16559286
申请日:2019-09-03
Applicant: Intel Corporation
Inventor: Zhichao ZHANG , Tao WU , Gaurav CHAWLA , Jeffrey LEE
IPC: H05K1/11
Abstract: A land grid array (LGA) land pad having reduced capacitance is disclosed. The conductive portion of a land pad that overlaps a parallel ground plane within the substrate is reduced by one or more non-conductive voids though the thickness of the conductive portion of the land pad. The voids may allow the contact area of the land pad, as defined by the perimeter of the land pad, to remain the same while reducing the conductive portion that overlaps the parallel ground plane. Capacitance between the land pad and the parallel ground plane is reduced by an amount proportional to the reduction in overlapping conductive area.
-
公开(公告)号:US20250004205A1
公开(公告)日:2025-01-02
申请号:US18216494
申请日:2023-06-29
Applicant: Intel Corporation
Inventor: Dekang CHEN , Nicholas PSAILA , Zhichao ZHANG , Eric J.M. MORET , Wesley B. MORGAN , Srikant NEKKANTY , Sang Yup KIM , Mohanraj PRABHUGOUD , Chao TIAN
Abstract: Multichannel optical assemblies for optical IO (input output) systems are provided. The optical assemblies comprise an optical isolator. In some examples the optical assemblies also comprise an array of GRIN lenses. In other examples, the optical assemblies also comprise micromirrors.
-
10.
公开(公告)号:US20230091050A1
公开(公告)日:2023-03-23
申请号:US17479031
申请日:2021-09-20
Applicant: Intel Corporation
Inventor: Zhichao ZHANG , Pooya TADAYON , Tarek A. IBRAHIM , Srinivas V. PIETAMBARAM , Changhua LIU , Kemal AYGÜN
IPC: G02B6/42
Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to optical interconnects and optical waveguides within a glass layer of a semiconductor package, where dies that are physically and optically coupled with the glass layer are optically coupled with each other via the optical waveguides. One or more reflectors may be used to direct the optical pathway through the glass layer. Other embodiments may be described and/or claimed.
-
-
-
-
-
-
-
-
-