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    HORIZONTAL PITCH TRANSLATION USING EMBEDDED BRIDGE DIES
    2.
    发明申请
    HORIZONTAL PITCH TRANSLATION USING EMBEDDED BRIDGE DIES 审中-公开

    公开(公告)号：US20200381350A1

    公开(公告)日：2020-12-03

    申请号：US16636620

    申请日：2017-09-29

    Applicant: Intel Corporation

    Inventor： Sujit SHARAN ,  Kemal AYGUN ,  Zhiguo QIAN ,  Yidnekachew MEKONNEN ,  Zhichao ZHANG ,  Jianyong XIE

    IPC: H01L23/498 ,  H01L23/00

    Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, wherein the die comprises a plurality of high density features. An interconnect bridge is embedded in the substrate, wherein the interconnect bridge may comprise a first region disposed on a surface of the interconnect bridge comprising a first plurality of features, wherein the first plurality of features comprises a first pitch. A second region disposed on the surface of the interconnect bridge comprises a second plurality of features comprising a second pitch, wherein the second pitch is greater than the first pitch.

    NOVEL CONNECTOR DESIGNS FOR PHOTONICS PACKAGING INTEGRATION
    5.
    发明申请
    NOVEL CONNECTOR DESIGNS FOR PHOTONICS PACKAGING INTEGRATION 有权

    公开(公告)号：US20220196935A1

    公开(公告)日：2022-06-23

    申请号：US17131682

    申请日：2020-12-22

    Applicant: Intel Corporation

    Inventor： Xiaoqian LI ,  Nitin DESHPANDE ,  Omkar KARHADE ,  Asako TODA ,  Divya PRATAP ,  Zhichao ZHANG

    IPC: G02B6/42

    Abstract: Embodiments disclosed herein include photonics packages. In an embodiment, a photonics package comprises a package substrate, and a compute die over the package substrate. In an embodiment, a photonics die is also over the package substrate, and the photonics die overhangs an edge of the package substrate. In an embodiment, an integrated heat spreader (IHS) is over the compute die and the photonics die, and a fiber connector is coupled to the photonics die. In an embodiment, the fiber connector is attached to the IHS

    PACKAGE LAND PAD IN CLOSED-LOOP TRACE FOR HIGH SPEED DATA SIGNALING
    6.
    发明申请
    PACKAGE LAND PAD IN CLOSED-LOOP TRACE FOR HIGH SPEED DATA SIGNALING 有权

    公开(公告)号：US20210305138A1

    公开(公告)日：2021-09-30

    申请号：US16828466

    申请日：2020-03-24

    Applicant: Intel Corporation

    Inventor： Zhichao ZHANG ,  Zhenguo JIANG ,  Haifa HARIRI ,  Kemal AYGÜN ,  Sriram SRINIVASAN

    IPC: H01L23/498 ,  H01R12/71

    Abstract: Embodiments disclosed herein include electronic packaged assemblies. In an embodiment, an electronic package comprises first and second surfaces. The second surface has a land pad in a land pad opening. The land pad is spaced away from the land pad opening by an outer gap. The land pad is a closed loop. In an embodiment, the electronic package is electrically coupled to a socket. The socket has an interconnect with a first connector and a second connector. The first connector of the interconnect is directly coupled to at least one portion of the closed loop. In an embodiment, when the first connector is coupled to at least two or more portions of the closed loop, the portions are spaced away from each other by a portion of the inner or outer gap. The closed loop comprises a conductive line continuously extending from a first end to a second end.

    REDUCED CAPACITANCE LAND PAD
    8.
    发明申请
    REDUCED CAPACITANCE LAND PAD 审中-公开

    公开(公告)号：US20190394876A1

    公开(公告)日：2019-12-26

    申请号：US16559286

    申请日：2019-09-03

    Applicant: Intel Corporation

    Inventor： Zhichao ZHANG ,  Tao WU ,  Gaurav CHAWLA ,  Jeffrey LEE

    IPC: H05K1/11

    Abstract: A land grid array (LGA) land pad having reduced capacitance is disclosed. The conductive portion of a land pad that overlaps a parallel ground plane within the substrate is reduced by one or more non-conductive voids though the thickness of the conductive portion of the land pad. The voids may allow the contact area of the land pad, as defined by the perimeter of the land pad, to remain the same while reducing the conductive portion that overlaps the parallel ground plane. Capacitance between the land pad and the parallel ground plane is reduced by an amount proportional to the reduction in overlapping conductive area.

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