公开(公告)号：US10540808B2

公开(公告)日：2020-01-21

申请号：US15267631

申请日：2016-09-16

Applicant: Intel Corporation

Inventor： Magnus Andersson ,  Robert M. Toth ,  Jon N Hasselgren ,  Tomas G. Akenine-Moller

IPC: G06T15/40 ,  G06T15/00 ,  G06T15/04

Abstract: Methods and apparatus relating to techniques for provision of hierarchical Z-Culling (HiZ) optimization for texture-dependent discard operations are described. In an embodiment, a processor performs one or more operations (such as HiZ or Hierarchical Stencil test) on depth data of an image tile in response to a determination that texture space bounds of the image tile is fully opaque. The processor performs the one or more operations regardless of whether a discard operation is enabled. Other embodiments are also disclosed and claimed.

公开(公告)号：US09754345B2

公开(公告)日：2017-09-05

申请号：US15060317

申请日：2016-03-03

Applicant: INTEL CORPORATION

Inventor： Tomas G Akenine-Moller ,  Jim K Nilsson ,  Prasoonkumar Surti ,  Jon N Hasselgren ,  Carl J Munkberg

IPC: G06K9/46 ,  G06T1/60 ,  G06T9/00 ,  G06T7/40 ,  G06T11/00 ,  G06T7/90

CPC classification number: G06T1/60 ,  G06K9/4652 ,  G06K2009/4666 ,  G06T7/90 ,  G06T9/00 ,  G06T11/00 ,  G06T2200/28 ,  G06T2207/20021

Abstract: Techniques related to graphics rendering including techniques for compression and/or decompression of graphics data by use of pixel region bit values are described.