公开(公告)号：US20180151733A1

公开(公告)日：2018-05-31

申请号：US15575011

申请日：2015-06-19

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  PATRICK H. KEYS ,  HAROLD W. KENNEL ,  RISHABH MEHANDRU ,  ANAND S. MURTHY ,  KARTHIK JAMBUNATHAN

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/167 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L27/0886 ,  H01L29/0603 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/167 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: Techniques are disclosed for forming p-MOS transistors having one or more carbon-based interface layers between epitaxially grown S/D regions and the channel region. In some cases, the carbon-based interface layer(s) may comprise a single layer having a carbon content of greater than 20% carbon and a thickness of 0.5-8 nm. In some cases, the carbon-based interface layer(s) may comprise a single layer having a carbon content of less than 5% and a thickness of 2-10 nm. In some such cases, the single layer may also comprise boron-doped silicon (Si:B) or boron-doped silicon germanium (SiGe:B). In some cases, one or more additional interface layers may be deposited on the carbon-based interface layer(s), where the additional interface layer(s) comprises Si:B and/or SiGe:B. The techniques can be used to improve short channel effects and improve the effective gate length of a resulting transistor.