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    TIN DOPED III-V MATERIAL CONTACTS
    6.
    发明申请
    TIN DOPED III-V MATERIAL CONTACTS 审中-公开
    TIN DOPED III-V材料联系

    公开(公告)号：US20150054031A1

    公开(公告)日：2015-02-26

    申请号：US14517365

    申请日：2014-10-17

    申请人： Intel Corporation

    发明人： GLENN A. GLASS ,  ANAND S. MURTHY ,  MICHAEL J. JACKSON ,  HAROLD W. KENNEL

    IPC分类号： H01L29/267 ,  H01L29/78 ,  H01L29/66 ,  H01L29/207 ,  H01L29/45

    CPC分类号： H01L29/267 ,  H01L21/28525 ,  H01L21/28568 ,  H01L29/165 ,  H01L29/207 ,  H01L29/42392 ,  H01L29/452 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/785 ,  H01L29/78696

    摘要： Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a metal contact such as one or more metals/alloys on silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example embodiment, an intermediate tin doped III-V material layer is provided between the source/drain and contact metal to significantly reduce contact resistance. Partial or complete oxidation of the tin doped layer can be used to further improve contact resistance. In some example cases, the tin doped III-V material layer has a semiconducting phase near the substrate and an oxide phase near the metal contact. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs, nanowire transistors, etc), as well as strained and unstrained channel structures.

    摘要翻译： 公开了用于形成相对于常规器件具有降低的寄生接触电阻的晶体管器件的技术。 这些技术可以例如使用诸如硅或硅锗（SiGe）源极/漏极区域上的一种或多种金属/合金的金属接触来实现。 根据一个示例性实施例，在源极/漏极和接触金属之间设置中间锡掺杂的III-V材料层，以显着降低接触电阻。 可以使用锡掺杂层的部分或完全氧化来进一步提高接触电阻。 在一些示例情况下，锡掺杂的III-V材料层在衬底附近具有半导体相和金属接触附近的氧化物相。 根据本公开，许多晶体管配置和合适的制造工艺将是显而易见的，包括平面和非平面晶体管结构（例如，FinFET，纳米线晶体管等）以及应变和非限制的通道结构。

    HIGH MOBILITY STRAINED CHANNELS FOR FIN-BASED NMOS TRANSISTORS
    7.
    发明申请
    HIGH MOBILITY STRAINED CHANNELS FOR FIN-BASED NMOS TRANSISTORS 审中-公开

    公开(公告)号：US20200381549A1

    公开(公告)日：2020-12-03

    申请号：US16998382

    申请日：2020-08-20

    申请人： INTEL CORPORATION

    发明人： STEPHEN M. CEA ,  ROZA KOTLYAR ,  HAROLD W. KENNEL ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  WILLY RACHMADY ,  TAHIR GHANI

    IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L27/092 ,  H01L29/04 ,  H01L29/06 ,  H01L29/161

    摘要： Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and cladding deposition can occur at a plurality of locations within typical process flow. In various embodiments, fins may be formed with a minimum width (or later thinned) so as to improve transistor performance. In some embodiments, a thinned fin also increases tensile strain across the core of a cladded fin. In some cases, strain in the core may be further enhanced by adding an embedded silicon epitaxial source and drain.

    HIGH MOBILITY STRAINED CHANNELS FOR FIN-BASED NMOS TRANSISTORS
    10.
    发明申请
    HIGH MOBILITY STRAINED CHANNELS FOR FIN-BASED NMOS TRANSISTORS 审中-公开

    公开(公告)号：US20190115466A1

    公开(公告)日：2019-04-18

    申请号：US16214946

    申请日：2018-12-10

    申请人： INTEL CORPORATION

    发明人： STEPHEN M. CEA ,  ROZA KOTLYAR ,  HAROLD W. KENNEL ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  WILLY RACHMADY ,  TAHIR GHANI

    IPC分类号： H01L29/78 ,  H01L29/161 ,  H01L29/04 ,  H01L29/06 ,  H01L27/092 ,  H01L29/10 ,  H01L29/66

    摘要： Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and cladding deposition can occur at a plurality of locations within typical process flow. In various embodiments, fins may be formed with a minimum width (or later thinned) so as to improve transistor performance. In some embodiments, a thinned fin also increases tensile strain across the core of a cladded fin. In some cases, strain in the core may be further enhanced by adding an embedded silicon epitaxial source and drain.