公开(公告)号：US20190013246A1

公开(公告)日：2019-01-10

申请号：US16068095

申请日：2016-03-28

Applicant: INTEL CORPORATION

Inventor： Charles H. WALLACE ,  Manish CHANDHOK ,  Paul A NYHUS ,  Eungnak HAN ,  Stephanie A. BOJARSKI ,  Florian GSTREIN ,  Gurpreet SINGH

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L27/02 ,  H01L29/08 ,  H01L29/78 ,  H01L21/308 ,  H01L29/165

Abstract: Aligned pitch-quartered patterning approaches for lithography edge placement error advanced rectification are described. For example, a method of fabricating a semiconductor structure includes forming a first patterned hardmask on a semiconductor substrate. A second hardmask layer is formed on the semiconductor substrate. A segregated di-block co-polymer is formed on the first patterned hardmask and on the second hardmask layer. Second polymer blocks are removed from the segregated di-block co-polymer. A second patterned hardmask is formed from the second hardmask layer and a plurality of semiconductor fins is formed in the semiconductor substrate using first polymer blocks as a mask. A first fin of the plurality of semiconductor fins is removed. Subsequent to removing the first fin, a second fin of the plurality of semiconductor fins is removed.