SPACER SELF-ALIGNED VIA STRUCTURES USING DIRECTED SELFASSEMBLY FOR GATE CONTACT OR TRENCH CONTACT

    公开(公告)号:US20230317617A1

    公开(公告)日:2023-10-05

    申请号:US17710827

    申请日:2022-03-31

    CPC classification number: H01L23/535 H01L21/76897

    Abstract: Spacer self-aligned via structures for gate contact or trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. The integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers between adjacent ones of the plurality of gate structures and the plurality of conductive trench contact structures, wherein the plurality of dielectric spacers protrudes above the plurality of gate structures and above the plurality of conductive trench contact structures. Individual ones of the plurality of dielectric spacers have an upper spacer portion on a lower spacer portion, with an interface between the upper spacer portion and the lower spacer portion.

    PLUG IN A METAL LAYER
    4.
    发明公开

    公开(公告)号:US20240113017A1

    公开(公告)日:2024-04-04

    申请号:US17958288

    申请日:2022-09-30

    CPC classification number: H01L23/528 H01L21/76892 H01L21/76837 H01L23/5226

    Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for forming a plug within a metal layer of a semiconductor device, where the plug is formed within a cavity that is created through the metal layer. The plug may extend through the metal layer and into a layer below the metal layer, which may be a layer that includes a dielectric and one or more electrical routing features. The plug may include an electrical insulator material. The cavity may be formed by placing a mask above the metal layer and performing an etch through the metal layer subsequently filled with a dielectric, where the plug will be tapered and wider at the top of the plug and become narrower as the plug continues through the metal layer and reaches the layer below the metal layer. Other embodiments may be described and/or claimed.

    DIFFERENTIATED MOLECULAR DOMAINS FOR SELECTIVE HARDMASK FABRICATION AND STRUCTURES RESULTING THEREFROM

    公开(公告)号:US20200058548A1

    公开(公告)日:2020-02-20

    申请号:US16347507

    申请日:2016-12-23

    Abstract: Selective hardmask-based approaches for conductive via fabrication are described. In an example, an integrated circuit structure includes a plurality of conductive lines in an inter-layer dielectric (ILD) layer above a substrate. The plurality of conductive lines includes alternating non-recessed conductive lines and recessed conductive lines. The non-recessed conductive lines are substantially co-planar with the ILD layer, and the recessed conductive lines are recessed relative to an uppermost surface of the ILD layer. A dielectric capping layer is in recess regions above the recessed conductive lines. A hardmask layer is over the non-recessed conductive lines but not over the dielectric capping layer of the recessed conductive lines. The hardmask layer differs in composition from the dielectric capping layer. A conductive via is in an opening in the dielectric capping layer and on one of the recessed conductive lines. A portion of the conductive via is on a portion of the hardmask layer.

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