公开(公告)号：US20240038661A1

公开(公告)日：2024-02-01

申请号：US18380466

申请日：2023-10-16

Applicant: Intel Corporation

Inventor： Manish CHANDHOK ,  Richard SCHENKER ,  Tristan TRONIC

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76846 ,  H01L23/53223 ,  H01L23/53266

Abstract: Integrated circuit (IC) structures, computing devices, and related methods are disclosed. An IC structure includes an interlayer dielectric (ILD), an interconnect, and a liner material separating the interconnect from the ILD. The interconnect includes a first end extending to or into the ILD and a second end opposite the first end. A second portion of the interconnect extending from the second end to a first portion of the interconnect proximate to the first end does not include the liner material thereon. A method of manufacturing an IC structure includes removing an ILD from between interconnects, applying a conformal hermetic liner, applying a carbon hard mask (CHM) between the interconnects, removing a portion of the CHM, removing the conformal hermetic liner to a remaining CHM, and removing the exposed portion of the liner material to the remaining CHM to expose the second portion of the interconnects.

公开(公告)号：US20220262722A1

公开(公告)日：2022-08-18

申请号：US17735006

申请日：2022-05-02

Applicant: Intel Corporation

Inventor： Richard E. SCHENKER ,  Robert L. BRISTOL ,  Kevin L. LIN ,  Florian GSTREIN ,  James M. BLACKWELL ,  Marie KRYSAK ,  Manish CHANDHOK ,  Paul A. NYHUS ,  Charles H. WALLACE ,  Curtis W. WARD ,  Swaminathan SIVAKUMAR ,  Elliot N. TAN

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L29/78

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

公开(公告)号：US20220238376A1

公开(公告)日：2022-07-28

申请号：US17720152

申请日：2022-04-13

Applicant: Intel Corporation

Inventor： Kevin LIN ,  Sudipto NASKAR ,  Manish CHANDHOK ,  Miriam RESHOTKO ,  Rami HOURANI

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L21/311 ,  H01L23/522 ,  H01L21/033

Abstract: Embodiments include an interconnect structure and methods of forming such an interconnect structure. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD) and a first interconnect layer with a plurality of first conductive traces partially embedded in the first ILD. In an embodiment, an etch stop layer is formed over surfaces of the first ILD and sidewall surfaces of the first conductive traces. In an embodiment, the interconnect structure further comprises a second interconnect layer that includes a plurality of second conductive traces. In an embodiment, a via between the first interconnect layer and the second interconnect layer may be self-aligned with the first interconnect layer.

公开(公告)号：US20190385897A1

公开(公告)日：2019-12-19

申请号：US16463816

申请日：2016-12-28

Applicant: INTEL CORPORATION

Inventor： Manish CHANDHOK ,  Sudipto NASKAR ,  Stephanie A. BOJARSKI ,  Kevin LIN ,  Marie KRYSAK ,  Tristan A. TRONIC ,  Hui Jae YOO ,  Jeffery D. BIELEFELD ,  Jessica M. TORRES

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: An integrated circuit die, a semiconductor structure, and a method of fabricating the semiconductor structure are disclosed. The integrated circuit die includes a substrate and a first anchor and a second anchor disposed on the substrate in a first plane. The integrated circuit die also includes a first wire disposed on the first anchor in the first plane, a third wire disposed on the second anchor in the first plane, and a second wire and a fourth wire suspended above the substrate in the first plane. The second wire is disposed between the first wire and the third wire and the third wire is disposed between the second wire and the fourth wire. The integrated circuit die further includes a dielectric material disposed between upper portions of the first wire, the second wire, the third wire, and the fourth wire to encapsulate an air gap.

公开(公告)号：US20190189500A1

公开(公告)日：2019-06-20

申请号：US16284568

申请日：2019-02-25

Applicant: Intel Corporation

Inventor： Manish CHANDHOK ,  Todd R. YOUNKIN ,  Eungnak HAN ,  Jasmeet S. CHAWLA ,  Marie KRYSAK ,  Hui Jae YOO ,  Tristan A. TRONIC

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/7682 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238

Abstract: A first etch stop layer is deposited on a plurality of conductive features on an insulating layer on a substrate. A second etch stop layer is deposited over an air gap between the conductive features. The first etch stop layer is etched to form a via to at least one of the conductive features.

公开(公告)号：US20240395815A1

公开(公告)日：2024-11-28

申请号：US18200967

申请日：2023-05-23

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Manish CHANDHOK ,  Tsuan-Chung CHANG ,  Robert JOACHIM ,  Peter NGUYEN ,  Lily MAO ,  Erik SKIBINSKI

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: Integrated circuit structures having metal-containing fin isolation regions are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires over a first sub-fin. A gate structure is over the vertical stack of horizontal nanowires and on the first sub-fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure but is on a second sub-fin. A gate cut is between the gate structure and the dielectric structure. A dielectric gate cut plug is in the gate cut. The dielectric gate plug includes a metal-containing dielectric material.

公开(公告)号：US20220199760A1

公开(公告)日：2022-06-23

申请号：US17129875

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Abhishek A. SHARMA ,  Noriyuki SATO ,  Sudarat LEE ,  Scott B. CLENDENNING ,  Sudipto NASKAR ,  Manish CHANDHOK ,  Hui Jae YOO ,  Van H. LE

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/528 ,  H01G4/10

Abstract: An integrated circuit (IC) structure having a plurality of backend double-walled capacitors (DWCs) are described. In an example, a first interconnect layer is disposed over a substrate and a second interconnect layer is disposed over the first interconnect layer. In the example, a plurality of DWCs are disposed in the first interconnect layer or the second interconnect layer to provide capacitance to assist the first interconnect layer and the second interconnect layer in providing electrical signal routing and power distribution to one or more devices in the IC structure. In examples, the IC structure includes a logic IC or a coupling substrate.

公开(公告)号：US20210091194A1

公开(公告)日：2021-03-25

申请号：US16579069

申请日：2019-09-23

Applicant: Intel Corporation

Inventor： Rami HOURANI ,  Richard VREELAND ,  Giselle ELBAZ ,  Manish CHANDHOK ,  Richard E. SCHENKER ,  Gurpreet SINGH ,  Florian GSTREIN ,  Nafees KABIR ,  Tristan A. TRONIC ,  Eungnak HAN

IPC: H01L29/423 ,  H01L29/78 ,  H01L23/522 ,  H01L29/417 ,  H01L21/8234 ,  H01L27/088

Abstract: Contact over active gate structures with metal oxide cap structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a metal oxide cap structure thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on a portion of one or more of the metal oxide cap structures.

公开(公告)号：US20210090990A1

公开(公告)日：2021-03-25

申请号：US16579077

申请日：2019-09-23

Applicant: Intel Corporation

Inventor： Rami HOURANI ,  Manish CHANDHOK ,  Richard E. SCHENKER ,  Florian GSTREIN ,  Leonard P. GULER ,  Charles H. WALLACE ,  Paul A. NYHUS ,  Curtis WARD ,  Mohit K. HARAN ,  Reken PATEL

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/02 ,  H01L23/66

Abstract: Contact over active gate structure with metal oxide layers are described are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A portion of one of the plurality of trench contact structures has a metal oxide layer thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on the metal oxide layer.

公开(公告)号：US20200185226A1

公开(公告)日：2020-06-11

申请号：US16334324

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Kevin LIN ,  Rahim KASIM ,  Manish CHANDHOK ,  Florian Gstrein

IPC: H01L21/302 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

Abstract: Techniques for selectively removing a metal or conductive material during processing of a semiconductor die for high-voltage applications are provided. In some embodiments, the techniques treat a metallized semiconductor die to transfer a feature from a patterned photoresist layer deposited on the metallized semiconductor die. In addition, the patterned metallized semiconductor die can be subjected to an etch process to remove an amount of metal according to the feature in the pattern, resulting in a treated metallized semiconductor die that defines an opening adjacent to at least a pair of neighboring metal interconnects in the die. The treated metallized semiconductor die can be further treated to backfill the opening with a dielectric material, resulting in a metallized semiconductor die having a backfilled dielectric member. Such a metallized semiconductor die can be further processed according to a process of record until metallization, after which additional selective removal of another amount of metal can be implemented. Semiconductor dies having neighboring metal interconnects separated by backfilled dielectric regions also are provided.