公开(公告)号：US20170345896A1

公开(公告)日：2017-11-30

申请号：US15525885

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： RASEONG KIM ,  UYGAR AVCI ,  IAN YOUNG

IPC: H01L29/06 ,  H01L29/775 ,  H01L29/66 ,  H01L29/423 ,  H01L29/16 ,  H01L29/786 ,  B82Y10/00

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L29/045 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Field effect transistor structures are described that are formed using germanium nanowires. In one example, the structure has a germanium nanowire formed on a substrate along a predetermined confinement orientation, a first doped region of the nanowire at a first end of the nanowire to define a source, a second doped region of the nanowire at a second end of the nanowire to define a drain, and a gate dielectric formed over the nanowire between the source and the drain.