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公开(公告)号：US20240363744A1
公开(公告)日：2024-10-31
申请号：US18139070
申请日：2023-04-25
发明人： Fu-Ting YEN , Yu-Yun PENG , Kuei-Lin CHAN
IPC分类号： H01L29/775 , H01L29/06 , H01L29/423 , H01L29/66
CPC分类号： H01L29/775 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66545
摘要： A semiconductor device includes a substrate, a first active structure, a second active structure, a wall and a STI layer. The first active structure is formed on the substrate. The second active structure is formed on the substrate. The wall is formed between the first active structure and the second active structure. The STI layer is formed adjacent to the first active structure and has an upper surface. A distance between a spacer of the first active structure and the upper surface of the STI layer may range between 0 and 50 nanometers.
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公开(公告)号：US20240363712A1
公开(公告)日：2024-10-31
申请号：US18505279
申请日：2023-11-09
发明人： Sang Moon Lee , Jin Bum Kim , Hyo Jin Kim , Yong Jun Nam , In Geon Hwang
IPC分类号： H01L29/423 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/08 , H01L29/66 , H01L29/775 , H01L29/786
CPC分类号： H01L29/42392 , H01L21/823807 , H01L21/823842 , H01L27/092 , H01L29/0673 , H01L29/0847 , H01L29/66439 , H01L29/66545 , H01L29/6656 , H01L29/775 , H01L29/78696
摘要： A semiconductor device may include a substrate, an active pattern extended in a first horizontal direction on the substrate, a plurality of nanosheets stacked and spaced apart from each other in a vertical direction on the active pattern, a gate electrode extended in a second horizontal direction different from the first horizontal direction on the active pattern, the gate electrode surrounding the plurality of nanosheets, a source/drain region on both sides of the plurality of nanosheets in the first horizontal direction on the active pattern, a gate insulating layer between the plurality of nanosheets and the gate electrode, and a doping layer between the plurality of nanosheets and the gate insulating layer, the doping layer including silicon (Si) or silicon germanium (SiGe) and doped with a doping material, at least a portion of the doping layer overlapping an uppermost nanosheet of the plurality of nanosheets in the first horizontal direction.
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3.发明公开公开(公告)号：US20240363491A1
公开(公告)日：2024-10-31
申请号：US18240675
申请日：2023-08-31
发明人： SEUNGCHAN YUN , WONHYUK HONG , PANJAE PARK , KANG-ILL SEO
IPC分类号： H01L23/48 , H01L21/768 , H01L21/8234 , H01L27/088 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
CPC分类号： H01L23/481 , H01L21/76898 , H01L21/823475 , H01L27/088 , H01L29/0673 , H01L29/41733 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a transistor comprising a source/drain region on a substrate; a backside power rail spaced apart from the source/drain region; and a power contact that is between the source/drain region and the backside power rail and electrically connects the source/drain region to the backside power rail. The substrate may be between the source/drain region and the backside power rail, and a centerline in a width direction of the source/drain region is angled with respect to a centerline in a width direction of the power contact.
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公开(公告)号：US20240355899A1
公开(公告)日：2024-10-24
申请号：US18234567
申请日：2023-08-16
发明人： Shen-Yang LEE , Chun-Da LIAO
IPC分类号： H01L29/51 , H01L29/06 , H01L29/40 , H01L29/423 , H01L29/66 , H01L29/775
CPC分类号： H01L29/516 , H01L29/0673 , H01L29/401 , H01L29/42392 , H01L29/66439 , H01L29/775
摘要： Embodiments provide a semiconductor device structure. The structure includes a semiconductor channel layer over a substrate, a gate dielectric layer disposed over the semiconductor channel layer. The gate dielectric layer includes a first high-K (HK) dielectric layer having a first dopant concentration of dipole elements, and a second HK dielectric layer having a second dopant concentration of dipole elements different than the first dopant concentration. The structure also includes a gate electrode layer deposited over the gate dielectric layer, and an insertion layer disposed between the gate dielectric layer and the gate electrode layer, wherein the insertion layer is formed of a noble metal.
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公开(公告)号：US20240355708A1
公开(公告)日：2024-10-24
申请号：US18304913
申请日：2023-04-21
发明人： Po-Yu HUANG , Shih-Chieh WU , Chen-Ming LEE , I-Wen WU , Fu-Kai YANG , Mei-Yun WANG
IPC分类号： H01L23/48 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
CPC分类号： H01L23/481 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L27/092 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/775 , H01L29/78696
摘要： One aspect of the present disclosure pertains to a method of forming a semiconductor device. The method includes forming a gate stack over a channel region and forming a first source/drain (S/D) trench adjacent the channel region and extending into the substrate below a top surface of an isolation structure. The method includes forming a first epitaxial S/D feature in the first S/D trench and forming a first frontside metal contact over the first epitaxial S/D feature. The method further includes forming a first backside trench that exposes a bottom surface of the first epitaxial S/D feature and forming a first backside conductive feature in the first backside trench and on the exposed bottom surface of the first epitaxial S/D feature. A top surface of the first backside conductive feature is under a bottommost surface of the gate stack.
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公开(公告)号：US20240347593A1
公开(公告)日：2024-10-17
申请号：US18292584
申请日：2022-02-17
发明人： Huilong Zhu
IPC分类号： H01L29/06 , H01L29/08 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
CPC分类号： H01L29/0673 , H01L29/0847 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/6656 , H01L29/775 , H01L29/78696
摘要： A nanowire/nanosheet device and a method of manufacturing the same, and an electronic apparatus including the nanowire/nanosheet device. The nanowire/nanosheet device includes: a substrate; a nanowire/nanosheet spaced apart from a surface of the substrate and extending in a first direction; a source/drain layer at opposite ends of the nanowire/nanosheet in the first direction and adjoining the nanowire/nanosheet; a gate stack extending in a second direction intersecting with the first direction to surround the nanowire/nanosheet; and a first spacer on a sidewall of the gate stack, wherein the first spacer includes a continuously extending material layer which has a first part along a surface of the nanowire/nanosheet, a second part along a sidewall of the source/drain layer facing the gate stack, and a third part along a sidewall of the gate stack facing the source/drain layer, and the second part and the third part have a seam or an interface therebetween.
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公开(公告)号：US20240347592A1
公开(公告)日：2024-10-17
申请号：US18135598
申请日：2023-04-17
发明人： Hong-Chih CHEN , Je-Wei HSU , Ting-Huan HSIEH , Chia-Hao KUO , Fu-Hsiang SU , Shih-Hsun CHANG , Ping-Chun WU
IPC分类号： H01L29/06 , H01L21/8234 , H01L27/092 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
CPC分类号： H01L29/0673 , H01L21/823418 , H01L27/092 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/775 , H01L29/78696
摘要： Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a source/drain region disposed over a substrate, a first interlayer dielectric layer surrounding a first portion of the source/drain region, a second interlayer dielectric layer distinct from the first interlayer dielectric layer surrounding a second portion of the source/drain region, a silicide layer disposed on the source/drain region, and a conductive contact disposed over the source/drain region. The conductive contact is disposed in the second interlayer dielectric layer.
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公开(公告)号：US20240347423A1
公开(公告)日：2024-10-17
申请号：US18298402
申请日：2023-04-11
发明人： Sagarika Mukesh , Shravana Kumar Katakam , Tao Li , Ruilong Xie , Nicholas Anthony Lanzillo , Julien Frougier
IPC分类号： H01L23/48 , H01L21/8234 , H01L27/088 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
CPC分类号： H01L23/481 , H01L21/823412 , H01L21/823475 , H01L27/088 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/775 , H01L29/78696
摘要： Embodiments of present invention provide a semiconductor structure. The structure includes an array of transistors on a semiconductor substrate, the array of transistors including a first transistor and a second transistor, the second transistor being next to the first transistor; and a metal connection between the first transistor and the second transistor, wherein the metal connection connects a first metal contact at a frontside of the array of transistors to a second metal contact at a backside of the array of transistors. A method of forming the same is also provided.
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公开(公告)号：US20240347105A1
公开(公告)日：2024-10-17
申请号：US18635268
申请日：2024-04-15
发明人： Jae-Joon KIM , Munhyeon KIM
IPC分类号： G11C11/419 , G11C5/06 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786 , H10B10/00
CPC分类号： G11C11/419 , G11C5/063 , H01L29/0673 , H01L29/41733 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696 , H10B10/125
摘要： A random access memory includes a first transistor including a first gate extending in a first direction, a second transistor disposed on a same plane as the first transistor and including a second gate extending in the first direction, a third transistor including a third gate extending in a second direction perpendicular to the first direction and formed on the first transistor, a fourth transistor including a fourth gate extending in the second direction and formed on the second transistor, a first storage node connecting the first gate of the first transistor to a drain of the third transistor and storing data, and a second storage node connecting the second gate of the second transistor to a drain of the fourth transistor and storing data.
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公开(公告)号：US20240339452A1
公开(公告)日：2024-10-10
申请号：US18297996
申请日：2023-04-10
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/06 , H01L29/08 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
CPC分类号： H01L27/0922 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L21/823878 , H01L29/0673 , H01L29/0847 , H01L29/41733 , H01L29/41775 , H01L29/42392 , H01L29/66439 , H01L29/6656 , H01L29/775 , H01L29/78696 , H01L29/66545
摘要： An air pocket is located between a top S/D region and a bottom S/D region of a stacked transistor. The air pocket reduces the parasitic capacitance between the top S/D region and the bottom S/D region, reduces the capacitance between the gate and the top S/D region, and/or reduces the capacitance between the gate and the bottom S/D region. Reduction of such capacitance(s) may improve performance of the semiconductor IC device and may allow for further semiconductor IC device scaling. A semiconductor IC device may include a bottom transistor and a top transistor. The top transistor may be vertically stacked, or aligned, with respect to the bottom transistor. The air pocket is located between, and may be vertically aligned with, the top S/D region and the bottom S/D region.
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