公开(公告)号：US20220103345A1

公开(公告)日：2022-03-31

申请号：US17547018

申请日：2021-12-09

Applicant: Intel Corporation

Inventor： Tomasz KANTECKI ,  Wei LI ,  Wajdi FEGHALI ,  James GUILFORD ,  Vinodh GOPAL

IPC: H04L9/06

Abstract: Methods, apparatus, and software for hashing data. The methods and apparatus employ novel improvements to hash algorithms, such as a SHA-2 hash algorithm to reduce computations and increase performance. In one aspect, calculation of SHA-2 message scheduling and SHA compression operations are separated under which an SHA-2 message schedule is applied to multiple rounds of SHA compression operations over multiple chunks of data for the data item being hashed. In another aspect, the SHA-2 message schedule is implemented such that message schedules for multiple message words or data blocks are performed in parallel. The approaches may be employed to reduce hash calculations for various purposes, including generating Filecoin nodes.

公开(公告)号：US20210351790A1

公开(公告)日：2021-11-11

申请号：US16872144

申请日：2020-05-11

Applicant: Intel Corporation

Inventor： James GUILFORD ,  Vinodh GOPAL ,  Dan CUTTER ,  Kirk YAP ,  Wajdi FEGHALI ,  George POWLEY

IPC: H03M7/30 ,  H03M7/46

Abstract: A lossless data compressor of an aspect includes a first lossless data compressor circuitry coupled to receive input data. The first lossless data compressor circuitry is to apply a first lossless data compression approach to compress the input data to generate intermediate compressed data. The apparatus also includes a second lossless data compressor circuitry coupled with the first lossless data compressor circuitry to receive the intermediate compressed data. The second lossless data compressor circuitry is to apply a second lossless data compression approach to compress at least some of the intermediate compressed data to generate compressed data. The second lossless data compression approach different than the first lossless data compression approach. Lossless data decompressors are also disclosed, as are methods of lossless data compression and decompression.

公开(公告)号：US20190310848A1

公开(公告)日：2019-10-10

申请号：US16452390

申请日：2019-06-25

Applicant: INTEL CORPORATION

Inventor： Vinodh GOPAL ,  Wajdi FEGHALI ,  Gilbert WOLRICH ,  Kirk YAP

IPC: G06F9/30

Abstract: An apparatus and method are described for performing efficient Boolean operations in a pipelined processor which, in one embodiment, does not natively support three operand instructions. For example, in one embodiment, a processor comprises: a set of registers for storing packed operands; Boolean operation logic to execute a single instruction which uses three or more source operands packed in the set of registers, the Boolean operation logic to read at least three source operands and an immediate value to perform a Boolean operation on the three source operands, wherein the Boolean operation comprises: combining a bit read from each of the three operands to form an index to the immediate value, the index identifying a bit position within the immediate value; reading the bit from the identified bit position of the immediate value; and storing the bit from the identified bit position of the immediate value in a destination register.

公开(公告)号：US20220224511A1

公开(公告)日：2022-07-14

申请号：US17710012

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Kamila LIPINSKA ,  Tomasz KANTECKI ,  Marcel CORNU ,  Pablo DE LARA GUARCH ,  Stephen MCINTYRE ,  Krystian MATUSIEWICZ ,  James GUILFORD ,  Vinodh GOPAL ,  Wajdi FEGHALI

IPC: H04L9/06 ,  H04L9/08 ,  G06F9/30

Abstract: Examples described herein relate to executing, on at least one processor, at least one Advanced Encryption Standard (AES) instruction, having an operation code (opcode), on operands, wherein execution of the at least one AES instruction generates an S1 box and/or S2 box of initialization and keystream generation for a SNOW3 cipher operation.

公开(公告)号：US20210149704A1

公开(公告)日：2021-05-20

申请号：US17127729

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Wajdi FEGHALI ,  Vinodh GOPAL ,  Kirk S. YAP ,  Sean GULLEY ,  Raghunandan MAKARAM

IPC: G06F9/455 ,  G06F12/14 ,  H04L9/08

Abstract: Systems, methods, and circuitries are disclosed for a per-process memory encryption system. At least one translation lookaside buffer (TLB) is configured to encode key identifiers for keys in one or more bits of either the virtual memory address or the physical address. The process state memory configured to store a first process key table for a first process that maps key identifiers to unique keys and a second process key table that maps the key identifiers to different unique keys. The active process key table memory configured to store an active key table. In response to a request for data corresponding to a virtual memory address, the at least one TLB is configured to provide a key identifier for the data to the active process key table to cause the active process key table to return the unique key mapped to the key identifier.