公开(公告)号：US20220091851A1

公开(公告)日：2022-03-24

申请号：US17029335

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： FANGFEI LIU ,  ALAA ALAMELDEEN ,  ABHISHEK BASAK ,  SCOTT CONSTABLE ,  FRANCIS MCKEEN ,  JOSEPH NUZMAN ,  CARLOS ROZAS ,  THOMAS UNTERLUGGAUER ,  XIANG ZOU

IPC: G06F9/38 ,  G06F9/48 ,  G06F21/54 ,  G06F9/30

Abstract: In one embodiment, a processor includes: a decode circuit to decode a load instruction that is to load an operand to a destination register, the decode circuit to generate at least one fencing micro-operation (μop) associated with the destination register; and a scheduler circuit coupled to the decode circuit. The scheduler circuit is to prevent speculative execution of one or more instructions that consume the operand in response to the at least one fencing μop. Other embodiments are described and claimed.

公开(公告)号：US20210200552A1

公开(公告)日：2021-07-01

申请号：US16728815

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： FANGFEI LIU ,  CARLOS ROZAS ,  THOMAS UNTERLUGGAUER ,  FRANCIS MCKEEN ,  ALAA ALAMELDEEN ,  Abhishek Basak ,  XIANG ZOU ,  RON GABOR ,  JIYONG YU

IPC: G06F9/38

Abstract: An apparatus and method for non-speculative resource deallocation. For example, one embodiment of a processor comprises: front-end circuitry comprising branch prediction circuitry to indicate a speculative instruction path and a fetch unit to fetch instructions from a memory or instruction cache in accordance with the speculative instruction path; an in-order queue coupled to the front end circuitry, the in-order queue to store instructions of the speculative instruction path provided from the front end circuitry; an out-of-order cluster comprising first instruction processing resources including allocation circuitry to allocate execution resources to be used to execute the instructions of the speculative instruction path and an instruction dispatcher to perform out-of-order dispatching of the instructions for execution; back-end circuitry comprising a plurality of functional units to execute the instructions of the speculative instruction path, the plurality of functional units to perform out-of-order execution of the instructions; and in-order resource deallocation circuitry to deallocate the first instruction processing resources in program order.