公开(公告)号：US20180004445A1

公开(公告)日：2018-01-04

申请号：US15201443

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： TOMER STARK ,  RON GABOR ,  JOSEPH NUZMAN

IPC: G06F3/06 ,  G06F12/14 ,  G06F12/06 ,  G06F11/07

CPC classification number: G06F12/0623 ,  G06F11/0727 ,  G06F11/073 ,  G06F12/14 ,  G06F2212/1052 ,  G06F2212/657

Abstract: One embodiment provides an apparatus. The apparatus includes a linear address space, metadata logic and enhanced address space layout randomization (ASLR) logic. The linear address space includes a metadata data structure. The metadata logic is to generate a metadata value. The enhanced ASLR logic is to combine the metadata value and a linear address into an address pointer and to store the metadata value to the metadata data structure at a location pointed to by a least a portion of the linear address. The address pointer corresponds to an apparent address in an enhanced address space. A size of the enhanced address space is greater than a size of the linear address space.

公开(公告)号：US20170161075A1

公开(公告)日：2017-06-08

申请号：US15021442

申请日：2015-06-01

Applicant: Intel Corporation

Inventor： ALEXANDR TITOV ,  DMITRY M. MASLENNIKOV ,  SERGEY Y. SHISHLOV ,  SERGEY P. SCHERBININ ,  VALENTIN A. BUROV ,  RON GABOR ,  DENIS G. MOTIN ,  OLEG SHIMKO ,  KAMIL GARIFULLIN ,  ALEXANDER V. BUTUZOV ,  EVGENIY N. PODKORYTOV ,  ANDREY CHUDNOVETS

IPC: G06F9/38 ,  G06F9/44 ,  G03F7/00 ,  G06F9/30 ,  G03F1/36 ,  G03F1/70

CPC classification number: G06F9/38 ,  G03F1/36 ,  G03F1/70 ,  G03F7/0005 ,  G06F8/445 ,  G06F9/30003 ,  G06F9/3017 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3889 ,  G06F9/44

Abstract: In an embodiment, a processor includes a plurality of cores. Each core may include strand logic to, for each strand of a plurality of strands, fetch an instruction group uniquely associated with the strand, wherein the instruction group is one of a plurality of instruction groups, wherein the plurality of instruction groups is obtained by dividing instructions of an application program according to instruction criticality. The strand logic may also be to retire the instruction group in an original order of the application program. Other embodiments are described and claimed.

公开(公告)号：US20170186498A1

公开(公告)日：2017-06-29

申请号：US15457326

申请日：2017-03-13

Applicant: Intel Corporation

Inventor： ASHOK RAJ ,  RON GABOR ,  HISHAM SHAFI ,  MOHAN J. KUMAR ,  THEODROS YIGZAW

IPC: G11C29/38 ,  G11C29/44

CPC classification number: G11C29/38 ,  G11C13/0004 ,  G11C29/04 ,  G11C29/44 ,  G11C29/52 ,  G11C2029/0401

Abstract: Methods and apparatuses relating to a hardware memory test unit to check a section of a data storage device for a transient fault before the data is stored in and/or loaded from the section of the data storage device are described. In one embodiment, an integrated circuit includes a hardware processor to operate on data in a section of a data storage device, and a memory test unit to check the section of the data storage device for a transient fault before the data is stored in the section of the data storage device, wherein the transient fault is to cause a machine check exception if accessed by the hardware processor.

公开(公告)号：US20190235938A1

公开(公告)日：2019-08-01

申请号：US16259736

申请日：2019-01-28

Applicant: Intel Corporation

Inventor： TOMER STARK ,  RON GABOR ,  JOSEPH NUZMAN

IPC: G06F11/07 ,  G06F12/06 ,  G06F12/14

CPC classification number: G06F11/073 ,  G06F11/0727 ,  G06F12/0623 ,  G06F12/14 ,  G06F2212/1052 ,  G06F2212/657

Abstract: One embodiment provides an apparatus. The apparatus includes a linear address space, metadata logic and enhanced address space layout randomization (ASLR) logic. The linear address space includes a metadata data structure. The metadata logic is to generate a metadata value. The enhanced ASLR logic is to combine the metadata value and a linear address into an address pointer and to store the metadata value to the metadata data structure at a location pointed to by a least a portion of the linear address. The address pointer corresponds to an apparent address in an enhanced address space. A size of the enhanced address space is greater than a size of the linear address space.

公开(公告)号：US20210200686A1

公开(公告)日：2021-07-01

申请号：US16728573

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： RON GABOR ,  RAANAN SADE ,  IGOR YANOVER ,  ASSAF ZALTSMAN ,  TOMER STARK

IPC: G06F12/1009 ,  G06F9/30

Abstract: An apparatus and method for tagged memory management. For example, one embodiment of a processor comprises: execution circuitry to execute instructions and process data, at least one instruction to generate a system memory access request having a first address pointer; and address translation circuitry to determine whether to translate the first address pointer with or without metadata processing, wherein if the first address pointer is to be translated with metadata processing, the address translation circuitry to: perform a lookup in a memory metadata table to identify a memory metadata value, determine a pointer metadata value associated with the first address pointer, and compare the memory metadata value with the pointer metadata value, the comparison to generate a validation of the memory access request or a fault condition, wherein if the comparison results in a validation of the memory access request, then accessing a set of one or more address translation tables to translate the first address pointer to a first physical address and to return the first physical address responsive to the memory access request.

公开(公告)号：US20210200684A1

公开(公告)日：2021-07-01

申请号：US16728527

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： RON GABOR ,  ENRICO PERLA ,  RAANAN SADE ,  IGOR YANOVER ,  TOMER STARK ,  JOSEPH NUZMAN

IPC: G06F12/0895 ,  G06F12/1081 ,  G06F12/1009 ,  G06F12/0811 ,  G06F12/14 ,  G06F9/30 ,  G06F11/30

Abstract: An apparatus and method for tagged memory management. For example, one embodiment of a processor comprises: execution circuitry to execute instructions and process data, at least one instruction to generate a system memory access request having a first address pointer; and address translation circuitry to determine whether to translate the first address pointer with or without metadata processing, wherein if the first address pointer is to be translated with metadata processing, the address translation circuitry to: perform a lookup in a memory metadata table to identify a memory metadata value, determine a pointer metadata value associated with the first address pointer, and compare the memory metadata value with the pointer metadata value, the comparison to generate a validation of the memory access request or a fault condition, wherein if the comparison results in a validation of the memory access request, then accessing a set of one or more address translation tables to translate the first address pointer to a first physical address and to return the first physical address responsive to the memory access request.

公开(公告)号：US20210200552A1

公开(公告)日：2021-07-01

申请号：US16728815

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： FANGFEI LIU ,  CARLOS ROZAS ,  THOMAS UNTERLUGGAUER ,  FRANCIS MCKEEN ,  ALAA ALAMELDEEN ,  Abhishek Basak ,  XIANG ZOU ,  RON GABOR ,  JIYONG YU

IPC: G06F9/38

Abstract: An apparatus and method for non-speculative resource deallocation. For example, one embodiment of a processor comprises: front-end circuitry comprising branch prediction circuitry to indicate a speculative instruction path and a fetch unit to fetch instructions from a memory or instruction cache in accordance with the speculative instruction path; an in-order queue coupled to the front end circuitry, the in-order queue to store instructions of the speculative instruction path provided from the front end circuitry; an out-of-order cluster comprising first instruction processing resources including allocation circuitry to allocate execution resources to be used to execute the instructions of the speculative instruction path and an instruction dispatcher to perform out-of-order dispatching of the instructions for execution; back-end circuitry comprising a plurality of functional units to execute the instructions of the speculative instruction path, the plurality of functional units to perform out-of-order execution of the instructions; and in-order resource deallocation circuitry to deallocate the first instruction processing resources in program order.

公开(公告)号：US20180060049A1

公开(公告)日：2018-03-01

申请号：US15615798

申请日：2017-06-06

Applicant: Intel Corporation

Inventor： DAVID J. SAGER ,  RUCHIRA SASANKA ,  RON GABOR ,  SHLOMO RAIKIN ,  JOSEPH NUZMAN ,  LEEOR PELED ,  JASON A. DOMER ,  HO-SEOP KIM ,  YOUFENG WU ,  KOICHI YAMADA ,  TIN-FOOK NGAI ,  HOWARD H. CHEN ,  JAYARAM BOBBA ,  JEFFREY J. COOK ,  OMAR M. SHAIKH ,  SURESH SRINIVAS

IPC: G06F9/45 ,  G06F11/36 ,  G06F9/38 ,  G06F9/54

Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.