公开(公告)号：US20230420514A1

公开(公告)日：2023-12-28

申请号：US17852016

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Chelsey DOROW ,  Sudarat LEE ,  Kevin P. O'BRIEN ,  Ande KITAMURA ,  Ashish Verma PENUMATCHA ,  Carl H. NAYLOR ,  Kirby MAXEY ,  Scott B. CLENDENNING ,  Uygar E. AVCI ,  Chia-Ching LIN

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/18 ,  H01L29/786 ,  H01L29/778

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/18 ,  H01L29/78696 ,  H01L29/778

Abstract: Embodiments disclosed herein include transistor devices. In an embodiment, the transistor comprises a transition metal dichalcogenide (TMD) channel. In an embodiment, a two dimensional (2D) dielectric is over the TMD channel. In an embodiment, a gate metal is over the 2D dielectric.

公开(公告)号：US20240006481A1

公开(公告)日：2024-01-04

申请号：US17853547

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Chelsey DOROW ,  Kevin P. O'BRIEN ,  Sudarat LEE ,  Ande KITAMURA ,  Ashish Verma PENUMATCHA ,  Carl H. NAYLOR ,  Kirby MAXEY ,  Chia-Ching LIN ,  Scott B. CLENDENNING ,  Uygar E. AVCI

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/6681 ,  H01L29/66545 ,  H01L29/78696

Abstract: Embodiments disclosed herein include transistors and methods of forming transistors. In an embodiment, the transistor comprises a source region, a drain region, a first semiconductor channel between the source region and the drain region, and a second semiconductor channel between the source region and the drain region over the first semiconductor channel. In an embodiment, an insulator is around the source region, the drain region, the first semiconductor channel, and the second semiconductor channel. In an embodiment, a first access hole is in the insulator adjacent to a first edge of the first semiconductor channel, and a second access hole is in the insulator adjacent to a second edge of the first semiconductor channel.