公开(公告)号：US20190041947A1

公开(公告)日：2019-02-07

申请号：US16022675

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Shankar Natarajan ,  Wayne Tran ,  Vishal Mannapur ,  Anthony Giardina

IPC: G06F1/32 ,  G06F13/42

Abstract: Technologies for dynamically managing a power state of a first endpoint device and a second endpoint device that are operatively coupled to a data bus of a compute device include communication monitor circuitry and power state manager circuitry. The communication monitor circuitry is configured to detect an activation signal on the data bus. The power state manager circuitry is configured to activate, in response to detection of the activation signal, the first and second endpoint devices that are operatively coupled to the data bus into a high power state from a low power state, determine, in response to activation of the first and second endpoint devices, which activated endpoint device is requested to perform work associated with the activation signal, and operate, in response to determination that the second endpoint device has no pending work to perform, the second endpoint device to return to the low power state.

公开(公告)号：US12259775B2

公开(公告)日：2025-03-25

申请号：US17323793

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Anthony Giardina

IPC: G06F1/329 ,  G06F1/3206 ,  G06F1/3234

Abstract: A timer intellectual property (IP) block that automatically determines an interval on which a processor circuitry is to be woken up to service periodic events, when it is given details about the requirements for those events (e.g., approximately how often they must occur, if it's important that they not happen too frequently or too infrequently, if the total number of events over a long average is important, etc.). For each periodic event that firmware must handle, the IP provides an Application Programming Interface (API) to register details of that event. The firmware configures all the events that it requires during system configuration, although it is possible to add, remove or modify individual events at runtime. At runtime, the optimized timer IP will interrupt the processor circuitry whenever one or more events need to be handled, based on a batching algorithm.

公开(公告)号：US20220374065A1

公开(公告)日：2022-11-24

申请号：US17323793

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Anthony Giardina

IPC: G06F1/329

Abstract: A timer intellectual property (IP) block that automatically determines an interval on which a processor circuitry is to be woken up to service periodic events, when it is given details about the requirements for those events (e.g., approximately how often they must occur, if it's important that they not happen too frequently or too infrequently, if the total number of events over a long average is important, etc.). For each periodic event that firmware must handle, the IP provides an Application Programming Interface (API) to register details of that event. The firmware configures all the events that it requires during system configuration, although it is possible to add, remove or modify individual events at runtime. At runtime, the optimized timer IP will interrupt the processor circuitry whenever one or more events need to be handled, based on a batching algorithm.